Commit 03476e68 authored by Lu Baolu's avatar Lu Baolu Committed by Jason Gunthorpe
Browse files

iommu/vt-d: Disallow read-only mappings to nest parent domain 

When remapping hardware is configured by system software in scalable mode
as Nested (PGTT=011b) and with PWSNP field Set in the PASID-table-entry,
it may Set Accessed bit and Dirty bit (and Extended Access bit if enabled)
in first-stage page-table entries even when second-stage mappings indicate
that corresponding first-stage page-table is Read-Only.

As the result, contents of pages designated by VMM as Read-Only can be
modified by IOMMU via PML5E (PML4E for 4-level tables) access as part of
address translation process due to DMAs issued by Guest.

This disallows read-only mappings in the domain that is supposed to be used
as nested parent. Reference from Sapphire Rapids Specification Update [1],
errata details, SPR17. Userspace should know this limitation by checking
the IOMMU_HW_INFO_VTD_ERRATA_772415_SPR17 flag reported in the IOMMU_GET_HW_INFO
ioctl.

[1] https://www.intel.com/content/www/us/en/content-details/772415/content-details.html

Link: https://lore.kernel.org/r/20231026044216.64964-9-yi.l.liu@intel.com


Reviewed-by: default avatarKevin Tian <kevin.tian@intel.com>
Signed-off-by: default avatarLu Baolu <baolu.lu@linux.intel.com>
Signed-off-by: default avatarYi Liu <yi.l.liu@intel.com>
Signed-off-by: default avatarJason Gunthorpe <jgg@nvidia.com>
parent b41e38e2

drivers/iommu/intel/iommu.c

+6 −0
Original line number Diff line number Diff line
@@ -2194,6 +2194,11 @@ __domain_mapping(struct dmar_domain *domain, unsigned long iov_pfn, 
	if ((prot & (DMA_PTE_READ|DMA_PTE_WRITE)) == 0)

		return -EINVAL;



	if (!(prot & DMA_PTE_WRITE) && domain->nested_parent) {

		pr_err_ratelimited("Read-only mapping is disallowed on the domain which serves as the parent in a nested configuration, due to HW errata (ERRATA_772415_SPR17)\n");

		return -EINVAL;

	}



	attr = prot & (DMA_PTE_READ | DMA_PTE_WRITE | DMA_PTE_SNP);

	attr |= DMA_FL_PTE_PRESENT;

	if (domain->use_first_level) {
@@ -4850,6 +4855,7 @@ static void *intel_iommu_hw_info(struct device *dev, u32 *length, u32 *type) 
	if (!vtd)

		return ERR_PTR(-ENOMEM);



	vtd->flags = IOMMU_HW_INFO_VTD_ERRATA_772415_SPR17;

	vtd->cap_reg = iommu->cap;

	vtd->ecap_reg = iommu->ecap;

	*length = sizeof(*vtd);

include/uapi/linux/iommufd.h

+11 −1
Original line number Diff line number Diff line
@@ -443,10 +443,20 @@ struct iommu_hwpt_alloc { 
};

#define IOMMU_HWPT_ALLOC _IO(IOMMUFD_TYPE, IOMMUFD_CMD_HWPT_ALLOC)



/**

 * enum iommu_hw_info_vtd_flags - Flags for VT-d hw_info

 * @IOMMU_HW_INFO_VTD_ERRATA_772415_SPR17: If set, disallow read-only mappings

 *                                         on a nested_parent domain.

 *                                         https://www.intel.com/content/www/us/en/content-details/772415/content-details.html

 */

enum iommu_hw_info_vtd_flags {

	IOMMU_HW_INFO_VTD_ERRATA_772415_SPR17 = 1 << 0,

};



/**

 * struct iommu_hw_info_vtd - Intel VT-d hardware information

 *

 * @flags: Must be 0

 * @flags: Combination of enum iommu_hw_info_vtd_flags

 * @__reserved: Must be 0

 *

 * @cap_reg: Value of Intel VT-d capability register defined in VT-d spec