Loading arch/mips/Kconfig +1 −1 Original line number Diff line number Diff line Loading @@ -807,7 +807,7 @@ config SIBYTE_CRHONE config SIBYTE_RHONE bool "Sibyte BCM91125E-Rhone" select BOOT_ELF32 select SIBYTE_BCM1125H select SIBYTE_SB1250 select SWAP_IO_SPACE select SYS_HAS_CPU_SB1 select SYS_SUPPORTS_BIG_ENDIAN Loading arch/mips/sibyte/Kconfig +0 −11 Original line number Diff line number Diff line Loading @@ -20,17 +20,6 @@ config SIBYTE_BCM1125 select SIBYTE_HAS_ZBUS_PROFILING select SIBYTE_SB1xxx_SOC config SIBYTE_BCM1125H bool select CEVT_SB1250 select CSRC_SB1250 select HAVE_PCI select IRQ_MIPS_CPU select SIBYTE_BCM112X select SIBYTE_ENABLE_LDT_IF_PCI select SIBYTE_HAS_ZBUS_PROFILING select SIBYTE_SB1xxx_SOC config SIBYTE_BCM112X bool select CEVT_SB1250 Loading Loading
arch/mips/Kconfig +1 −1 Original line number Diff line number Diff line Loading @@ -807,7 +807,7 @@ config SIBYTE_CRHONE config SIBYTE_RHONE bool "Sibyte BCM91125E-Rhone" select BOOT_ELF32 select SIBYTE_BCM1125H select SIBYTE_SB1250 select SWAP_IO_SPACE select SYS_HAS_CPU_SB1 select SYS_SUPPORTS_BIG_ENDIAN Loading
arch/mips/sibyte/Kconfig +0 −11 Original line number Diff line number Diff line Loading @@ -20,17 +20,6 @@ config SIBYTE_BCM1125 select SIBYTE_HAS_ZBUS_PROFILING select SIBYTE_SB1xxx_SOC config SIBYTE_BCM1125H bool select CEVT_SB1250 select CSRC_SB1250 select HAVE_PCI select IRQ_MIPS_CPU select SIBYTE_BCM112X select SIBYTE_ENABLE_LDT_IF_PCI select SIBYTE_HAS_ZBUS_PROFILING select SIBYTE_SB1xxx_SOC config SIBYTE_BCM112X bool select CEVT_SB1250 Loading