Commit 0272b9c3 authored by Marijn Suijten's avatar Marijn Suijten Committed by Dmitry Baryshkov
Browse files

drm/msm/dpu: Add TEAR-READ-pointer interrupt to INTF block 



All SoCs since DPU 5.0.0 have the tear interrupt registers moved out of
the PINGPONG block and into the INTF block.  The new interrupts are
described in dpu_hw_interrupts.c, now wire them up in individual SoC
catalog files by setting the intr_tear_rd_ptr to the IRQ index spcified
in the offset table and enabling this set of DPU interrupts via the
mdss_irqs bitmask.

Signed-off-by: default avatarMarijn Suijten <marijn.suijten@somainline.org>
Reviewed-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/534236/
Link: https://lore.kernel.org/r/20230411-dpu-intf-te-v4-19-27ce1a5ab5c6@somainline.org


Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
parent ec6e9b67

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h

+8 −4
Original line number Diff line number Diff line
@@ -165,12 +165,14 @@ static const struct dpu_intf_cfg sm8150_intf[] = { 
	INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, 0, 24, INTF_SC7180_MASK,

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)),

	INTF_BLK("intf_1", INTF_1, 0x6a800, 0x2bc, INTF_DSI, 0, 24, INTF_SC7180_MASK,

	INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2bc, INTF_DSI, 0, 24, INTF_SC7180_MASK,

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27)),

	INTF_BLK("intf_2", INTF_2, 0x6b000, 0x2bc, INTF_DSI, 1, 24, INTF_SC7180_MASK,

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),

			DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)),

	INTF_BLK_DSI_TE("intf_2", INTF_2, 0x6b000, 0x2bc, INTF_DSI, 1, 24, INTF_SC7180_MASK,

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29)),

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),

			DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2)),

	INTF_BLK("intf_3", INTF_3, 0x6b800, 0x280, INTF_DP, 1, 24, INTF_SC7180_MASK,

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31)),
@@ -234,7 +236,9 @@ const struct dpu_mdss_cfg dpu_sm8150_cfg = { 
		     BIT(MDP_SSPP_TOP0_HIST_INTR) | \

		     BIT(MDP_INTF0_INTR) | \

		     BIT(MDP_INTF1_INTR) | \

		     BIT(MDP_INTF1_TEAR_INTR) | \

		     BIT(MDP_INTF2_INTR) | \

		     BIT(MDP_INTF2_TEAR_INTR) | \

		     BIT(MDP_INTF3_INTR) | \

		     BIT(MDP_AD4_0_INTR) | \

		     BIT(MDP_AD4_1_INTR),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h

+8 −4
Original line number Diff line number Diff line
@@ -166,12 +166,14 @@ static const struct dpu_intf_cfg sc8180x_intf[] = { 
	INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7180_MASK,

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)),

	INTF_BLK("intf_1", INTF_1, 0x6a800, 0x2bc, INTF_DSI, 0, 24, INTF_SC7180_MASK,

	INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2bc, INTF_DSI, 0, 24, INTF_SC7180_MASK,

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27)),

	INTF_BLK("intf_2", INTF_2, 0x6b000, 0x2bc, INTF_DSI, 1, 24, INTF_SC7180_MASK,

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),

			DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)),

	INTF_BLK_DSI_TE("intf_2", INTF_2, 0x6b000, 0x2bc, INTF_DSI, 1, 24, INTF_SC7180_MASK,

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29)),

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),

			DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2)),

	/* INTF_3 is for MST, wired to INTF_DP 0 and 1, use dummy index until this is supported */

	INTF_BLK("intf_3", INTF_3, 0x6b800, 0x280, INTF_DP, 999, 24, INTF_SC7180_MASK,

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
@@ -240,7 +242,9 @@ const struct dpu_mdss_cfg dpu_sc8180x_cfg = { 
		     BIT(MDP_SSPP_TOP0_HIST_INTR) | \

		     BIT(MDP_INTF0_INTR) | \

		     BIT(MDP_INTF1_INTR) | \

		     BIT(MDP_INTF1_TEAR_INTR) | \

		     BIT(MDP_INTF2_INTR) | \

		     BIT(MDP_INTF2_TEAR_INTR) | \

		     BIT(MDP_INTF3_INTR) | \

		     BIT(MDP_INTF4_INTR) | \

		     BIT(MDP_INTF5_INTR) | \

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h

+8 −4
Original line number Diff line number Diff line
@@ -166,12 +166,14 @@ static const struct dpu_intf_cfg sm8250_intf[] = { 
	INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, 0, 24, INTF_SC7180_MASK,

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)),

	INTF_BLK("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, 0, 24, INTF_SC7180_MASK,

	INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, 0, 24, INTF_SC7180_MASK,

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27)),

	INTF_BLK("intf_2", INTF_2, 0x6b000, 0x2c0, INTF_DSI, 1, 24, INTF_SC7180_MASK,

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),

			DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)),

	INTF_BLK_DSI_TE("intf_2", INTF_2, 0x6b000, 0x2c0, INTF_DSI, 1, 24, INTF_SC7180_MASK,

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29)),

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),

			DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2)),

	INTF_BLK("intf_3", INTF_3, 0x6b800, 0x280, INTF_DP, 1, 24, INTF_SC7180_MASK,

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31)),
@@ -242,7 +244,9 @@ const struct dpu_mdss_cfg dpu_sm8250_cfg = { 
		     BIT(MDP_SSPP_TOP0_HIST_INTR) | \

		     BIT(MDP_INTF0_INTR) | \

		     BIT(MDP_INTF1_INTR) | \

		     BIT(MDP_INTF1_TEAR_INTR) | \

		     BIT(MDP_INTF2_INTR) | \

		     BIT(MDP_INTF2_TEAR_INTR) | \

		     BIT(MDP_INTF3_INTR) | \

		     BIT(MDP_INTF4_INTR),

};

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h

+5 −3
Original line number Diff line number Diff line
@@ -88,9 +88,10 @@ static const struct dpu_intf_cfg sc7180_intf[] = { 
	INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7180_MASK,

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)),

	INTF_BLK("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, 0, 24, INTF_SC7180_MASK,

	INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, 0, 24, INTF_SC7180_MASK,

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27)),

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),

			DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)),

};



static const struct dpu_wb_cfg sc7180_wb[] = {
@@ -152,7 +153,8 @@ const struct dpu_mdss_cfg dpu_sc7180_cfg = { 
		     BIT(MDP_SSPP_TOP0_INTR2) | \

		     BIT(MDP_SSPP_TOP0_HIST_INTR) | \

		     BIT(MDP_INTF0_INTR) | \

		     BIT(MDP_INTF1_INTR),

		     BIT(MDP_INTF1_INTR) | \

		     BIT(MDP_INTF1_TEAR_INTR),

};



#endif

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h

+5 −3
Original line number Diff line number Diff line
@@ -67,9 +67,10 @@ static const struct dpu_pingpong_cfg sm6115_pp[] = { 


static const struct dpu_intf_cfg sm6115_intf[] = {

	INTF_BLK("intf_0", INTF_0, 0x00000, 0x280, INTF_NONE, 0, 0, 0, 0, 0),

	INTF_BLK("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, 0, 24, INTF_SC7180_MASK,

	INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, 0, 24, INTF_SC7180_MASK,

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27)),

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),

			DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)),

};



static const struct dpu_perf_cfg sm6115_perf_data = {
@@ -124,7 +125,8 @@ const struct dpu_mdss_cfg dpu_sm6115_cfg = { 
	.mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \

		     BIT(MDP_SSPP_TOP0_INTR2) | \

		     BIT(MDP_SSPP_TOP0_HIST_INTR) | \

		     BIT(MDP_INTF1_INTR),

		     BIT(MDP_INTF1_INTR) | \

		     BIT(MDP_INTF1_TEAR_INTR),

};



#endif