Fix FIRRTL direction calculations for Vec and OpaqueType

Similarly to Vecs, both the direction of the OpaqueType itself and the
direction of its element can affect the direction of the resulting
firrtl port. Since OpaqueTypes can wrap other OpaqueTypes, this
direction calculation needs to be recursive. The same basic principle
applies to calculating firrtl flip for OpaqueTypes that are elements of
other Records.

For ports of type Vec, the direction of both the Vec itself and the
direction of its elements can affect the direction of the FIRRTL port.
Previously, we did not handle the fact that the Vec's elements could,
themselves, be Vecs, thus making this directionality calculation
recursive. Also, the logic was only applying to regular RawModules and
Modules. The fix now applies to BlackBoxes and ExtModules as well.

* Publish website to gh-pages branch (#2950)
* Update website/README.md

Records now have auto cloneType always enabled.
chisel3.experimental.AutoCloneType is deprecated.

Co-authored-by: Jack Koenig <koenig@sifive.com>

Add FIRRTL Intrinsic support with CIRCT sizeOf intrinsic.

Remove the default option of "-verify-each=false" to firtool.  This
shouldn't be necessary and shouldn't be turned on.  I had left this on
when doing some performance comparisons and it made its way into
upstream chisel.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Bring the website (chisel5) in as git subtree

- update README to have proper links to this version of the code
- Move website CI script to top level workflows, give some more unique names
- remove chisel3 submodule dependency from website
- website: Tweak to build within chisel3
- Add firtool as a dependency in CI and the README for the website
- website: remove dependabot file since we have no submodules
- add website to required CI checks

Update .github/workflows/test.yml

Co-authored-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

git-subtree-dir: website
git-subtree-mainline: b67a1adf
git-subtree-split: 160a018e

* Add deprecations
* Update build.sbt with warning suppression
* Move requireIsHardware and requireIsChiselType

Co-authored-by: Jack Koenig <koenig@sifive.com>

Co-authored-by: Jack Koenig <koenig@sifive.com>

Bumps [chiseltest](https://github.com/ucb-bar/chisel-testers2) from `1216ddc` to `82df8ed`.
- [Release notes](https://github.com/ucb-bar/chisel-testers2/releases)
- [Commits](https://github.com/ucb-bar/chisel-testers2/compare/1216ddce9217c8b4ae1134eda0ad929e63c5c185...82df8ed030755d3f5fefcdfbcdebe7a00650d494

)

---
updated-dependencies:
- dependency-name: chiseltest
  dependency-type: direct:production
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Bumps [firrtl](https://github.com/freechipsproject/firrtl) from `01e567d` to `e97c7b1`.
- [Release notes](https://github.com/freechipsproject/firrtl/releases)
- [Commits](https://github.com/freechipsproject/firrtl/compare/01e567de5d8e50d4bcb784eae45651da71fe6efd...e97c7b1aac5d095afc07f090f9b161e632db6bf8

)

---
updated-dependencies:
- dependency-name: firrtl
  dependency-type: direct:production
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Bumps [chisel3](https://github.com/freechipsproject/chisel3) from `9a7945fd` to `135594a1`.
- [Release notes](https://github.com/freechipsproject/chisel3/releases)
- [Commits](https://github.com/freechipsproject/chisel3/compare/9a7945fd86fcad02da0556d8f4a30daa4b005f9d...135594a13e97839007d199a8e6f77ee5776da857

)

---
updated-dependencies:
- dependency-name: chisel3
  dependency-type: direct:production
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* assert{Inferred,Known}Width: tweak to support width of zero.

Can't create -1.S(0.W), special-case zero-width.

* Bits: nicer error messages for zero-width

* Support zero-width integer literals.

These are in the FIRRTL language specification now
and supported by both SFC + MFC.

For SInt, special-case handle zero-width as not needing a sign bit.

Zero-width literals must be explicitly zero-width (`0.U(0.W)`);
literals such as `0.U` are (still) at least 1-bit.

* check zero-width to bool conversion

* onehot test

* UIntOps: test a few operations.

* SIntOps: test a few operations

* {S,U}IntOps: touchup test description, now includes head/tail/pad.

* ChiselSpec: Fix assert{Known,Inferred}Width for zero-width.

Specifically, fix the inferred-width check.

Start from zero-width literal, otherwise 0.U will need 1 bit.

* WidthSpec: update inferred zero-width test

We had implemented equals, but not hashCode. This commit also changes
the implemental of equals to just use the underlying values instead of
wasting the compute calling .toString.

Delete TruthTable.sort, it is unused.

* Change tests to use import circt.stage.ChiselStage instead
of chisel3.stage.ChiselStage. These are the tests that are trivially
done via
emitChirrtl -> emitChirrtl
emitFirrtl  -> emitChirrtl
emitVerilog -> emitSystemVerilog

* scalafmt

* Fixes for review comments

They are commonly used and if we were ever to change them, we will need
to go through a deprecation process anyway.

Note that the EnumAnnotations remain in chisel3.experimental because,
like all Chisel annotation support, they are slated to be deprecated and
removed.

Bumps [chisel3](https://github.com/freechipsproject/chisel3) from `116210ff` to `9a7945fd`.
- [Release notes](https://github.com/freechipsproject/chisel3/releases)
- [Commits](https://github.com/freechipsproject/chisel3/compare/116210ff806ccdda91b4c3343f78bad66783d0e6...9a7945fd86fcad02da0556d8f4a30daa4b005f9d

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  dependency-type: direct:production
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