- fix interval lit emission, upper and lower bound are the same as value
- Some cosmetic line length changes in Bits.scala in Interval code
- More tests for IntevalSpec
- Some basic cleanup of IntervalSpec
- Create some utilities for testing Intervals in Util
- Cleanup in Bits
  - break up long lines in Interval
  - clean up some stale comments
  - added more scaladoc on interval methods
  - added some more object utility methods for interacting with BigDecimal

Some firrtl imports were changed to use constraints package
wrap has become squeeze

- move to Scala 2.12.6 since everything else has
- Fix lack of type signature on LitOption in Aggregate.scala
  - made it match underlying data signature

- RegInit requires width to avoid un-inferred width
- Need to set wire used for Interval inference to be set to DontCare

- Acceded to request to import reflective calls by warnings
- Tests often need updating with `DontCare`s
- IntervalChainedSubTester works on Treadle not in verilator right now
- Bit width of range"[0,0]" is 1
- Added DontCare to valid connect argument for Interval
- Use binary point (when known) to shiftRight computation on Interval

-

- In converter literals get known bounds
- WIP on IntervalSpec
- Bits, hacking to get toType correct, still not there yet

- Still trying to get asInterval right

- Converter knows about them
- Emitter knows how to emit them
- Type maps added to package object
- Add IntervalSpec
- Re-work RangeSpec
- Add Interval type to Bits
- Data knows hot to clone them
- MonoConnect can connect them
- core package knows about literal creation
- IR knows about them
- IR gets RangeType
- RangeTransform modernized

This adds an annotator that provides a linkage to the FIRRTL
WiringTransform. This enables synthesizable cross module references
between one source and multiple sinks without changing IO (the
WiringTransform bores through the hierarchy).

Per WiringTransform, this will connect sources to their closest
sinks (as determined by BFS) or fail if ownership is indeterminate.

Make TesterDriver.execute work like Driver.execute:
  - annotations are included when running FIRRTL
  - custom transforms are run automatically

Also, add a bore method to BoringUtils that allows you to do one source to
multi-sink mapping in a single call. This adds a test that this is doing
the same thing as the equivalent call via disjoint addSink/addSource.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

Fixes #852

See https://github.com/freechipsproject/chisel3/issues/867 for future API discussion

Add support for Input() and Output() (available in Chisel2 since ucb-bar/chisel2-deprecated#734) and test for same.

They should not be deprecated until zero-width wires actually work

binding => topBinding so that partial Bundles work and undefined Bundle members properly forward to DontCareBinding

This shows errors comparing literals