Re-worked example of AnalyzeCircuit test to show how to capture output for testing purposes

This is an odd one.  Using log2Ceil directly results in a Verilator
compile error, presumably due to a FIRRTL zero-width wire bug.

The old implementation failed to check for width <= -2, and
did the wrong thing when -1 was explicitly passed.  Splitting
into two methods avoids the latter issue.

log2Ceil's argument might be 1, so employ a max operator.

Since the argument is at least 2, this change has no semantic effect.

Since the argument is at least 2, this change has no semantic effect.

Both should be zero-width wires.

Provide a better error message when length < 0.

Change log2Up in log2Ceil, which has no effect, since the argument
is always at least 2.

It always should throw an exception when n < 0, but in the specific
case of x.isWidthKnown && x.getWidth == 1, it failed to do so.

This commit also changes log2Up in log2Ceil, which has no effect,
since the argument is always at least 2.

* Use test_run_dir for more tests.

* Use official option and DRY.

Make "test_run_dir" the default for ChiselSpec.
Verify output files are created in DriverSpec tests.

This is necessary for user-defined Record-derived types to retain
the same signal name as they would using a Vec.

Fixes #501. Also added UIntOps test.

Test for ucb-bar/firrtl#407

This turned up after updating #494 (Remove explicit import of NotStrict) and adding the missing implicit CompileOptions to ":="'s signature at which point Scala pointed out FixedPoint's ":=" could not override Data's final ":=" with the same signature: the implicit time bomb.

* Bugfix #513. Needs better test case

* Improved test

* change builder for bundle reflection fix

* fixed bug -- should be not assignable

* Add scaladoc examples for Vec and Bundle

* address comments, added @example tag
eliminate extraneous context

* address comments, added @example tag
eliminate extraneous context

* ok, I've wrestled with the javadoc sytnax, the following commit, is my best result so far

withClockAndReset, withReset, and withClock allow changing the implicit clock and reset.
Module.clock and Module.reset provide access to the current implicit clock and reset.

* Don't allow analog to analog monoconnect
adjust tests accordingly

* demonstrate bit loss in shift right for fixed point

* cleaned up some stuff.
this does not test clean due to bug in firrtl

Used for stitching Verilog inout through Chisel Modules (from BlackBox
to BlackBox)