Co-authored-by: Jiuyang Liu <liu@jiuyang.me>
Co-authored-by: Jack Koenig <koenig@sifive.com>

Add a wrapper API around a handful of new CIRCT compiler intrinsics that
allow for FIRRTL inputs to express linear temporal logic expressions and
assert, assume, and cover operations on them. The CIRCT compiler emits
these as SVAs.

Since there are no opaque user-defined types in FIRRTL yet, the
intrinsics all use `UInt<1>` as the type for sequences and properties.
This change exposes a safe Chisel API with `Sequence` and `Property`
wrappers around the internal `UInt<1>` types.

As FIRRTL and the CIRCT compiler evolve, we'll be able to use more
strongly-typed intrinsics and later probably dedicated FIRRTL IR nodes
for this. I also expect the `circt.verif.assert` intrinsics to be
collapsed with the other assertion mechanisms in FIRRTL to provide one
uniform IR node. That's future work though. This commit just gets the
ball rolling.

* Update Chisel Dev Meeting time
* Update some uses of 5.0.0-RC1 to 5.0.0

* Remove support for Scala 2.12

* clean up mill build.

---------

Co-authored-by: Jiuyang Liu <liu@jiuyang.me>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

* Allow IntrinsicModule to be used in Instantiate

Change a few `RawModule`s to `BaseModule`s to allow for intrinsic
modules to be used with the instantiation API.

* Add tests for Instantiate of non-RawModules

---------

Co-authored-by: Fabian Schuiki <fabian@schuiki.ch>

This enables Chisel users to use these newer Scala versions.

Fix up code underlying `compile` used in many tests to
put annotations at the head of chirrtl
removed writing of WriteOutputAnnotations
removed passing in of json created by WriteOutputAnnotations files to firtool
Moved two tests in TraceSpec to use in instead of ignore

Fix a bug in BoringUtils (and secret IO APIs) where APIs would return a
Data.  This could create problems if the BoringUtils APIs were used
directly in operations, e.g., the following could cause a problem:

    val a = b & BoringUtils.bore(c)

This requires some casting of DontCare as it is unfortunately not a proper
"bottom" type.

No test is added as the test is that Scala passes type checking.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

The updated versions fix warnings about deprecated actions.

Change FIRRTL emission to use a simpler syntax for registers without a
reset.  Previously, this used a self-reset with a zero reset signal.
Simplify this to emit a register without a reset.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Co-authored-by: Jack Koenig <koenig@sifive.com>