Bump version

```
[error] .../chisel3/src/main/scala/chisel3/util/ImplicitConversions.scala:16:50: type mismatch;
[error]  found   : x.type (with underlying type Boolean)
[error]  required: ?{def asBool: ?}
[error] Note that implicit conversions are not applicable because they are ambiguous:
[error]  both method fromBooleanToLiteral in package chisel3 of type (x: Boolean)chisel3.package.fromBooleanToLiteral
[error]  and method booleanToBool in object ImplicitConversions of type (x: Boolean)chisel3.Bool
[error]  are possible conversion functions from x.type to ?{def asBool: ?}
[error]   implicit def booleanToBool(x: Boolean): Bool = x.asBool
```

This bumps scopt from 3.6.0 to 3.7.0 to align with FIRRTL. FIRRTL
requires 3.7.0+ for added scopt methods that allow introspection
of options (e.g., examing the short options of a long option).
This bump avoids a compile-time warning due to the version
mistmatch.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
(cherry picked from commit 69d247be)

Now that Chisel3 has been released, you only need local Chisel to use the master branch in a project.

(cherry picked from commit dd82374f)

Fixes #893

(cherry picked from commit 2f40920b)

(cherry picked from commit abee251c)

(cherry picked from commit 2ce78878)

Resolves #917

(cherry picked from commit a6f22d46)

This wraps the evaluation of BaseModule.name in try/catch to look for a
NullPointerException that may result from trying to evaluate desiredName
before it's ready. This catches a test case of using a desiredName that
depends on a later defined eager subinstance.

h/t @jackkoenig

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
(cherry picked from commit f64388e7)

* Modify noenq to set the input wires to DontCare.

(cherry picked from commit b87e6cf6)

(cherry picked from commit c316a0a2)

(cherry picked from commit 07482788)

Use BlackBoxSourceHelper.fileListName instead of hard-coding string.
Curious Decoupled requireIsChiselType failure - hdtew.

* Ability to load memories at simulation startup
* first pass
* create annotation
* create skeleton Transform

* Work in progress
Building out transform and pass now

* Support for LoadMemory annotation
* Creates chisel and firrtl LoadMemory annotations
* LoadMemoryTransform converts annotation into BlackBox InLine
* Simple test that verilog bound modules get created.

* Support for LoadMemory annotation
* Supports Bundled/multi-field memories
* more tests
* support for `$readmemh` and `$readmemb`
* warns if suffix used in file specification.

* Support for LoadMemory annotation
* Use standard chisel annotation idiom

* Support for LoadMemory annotation
* Fixes for @seldridge nits and super-nits

* Support for LoadMemory annotation
- transform now only runs if emitter is an instance of VerilogEmitter
- suffixes on memory text files are now respected
  - if suffix exists and memory is aggregate, aggregate sub-fields will now be inserted before suffix
- every bind module created gets a unique number
  - this is required when multiple loaded memories appear in a module
  - this should be generalized for other uses of binding modules

* Support for LoadMemory annotation
- remove un-needed suffix test

* Support for LoadMemory annotation
- remove instance walk, now just processes each module

* Support for LoadMemory annotation
- Move LoadMemoryTransformation into Firrtl for treadle to access it.

* Support for LoadMemory annotation
- One more bug in suffix handling has been eliminated

* Support for LoadMemory annotation
- remove unused findModule per jackkoenig
- fixed complex test, bad filename edge case

* Support for LoadMemory annotation
- changed to not use intellij style column alignment for : declarations

* Load memory from file
Fixes based on @jkoenig review
- remove unused BindPrefixFactory
- Moved code from CreateBindableMemoryLoaders into to LoadMemoryTransfrom
- Made map to find relevant memory annotations faster
- Made map to find modules referenced by annotations faster
- Made things private that should be private
- DefAnnotatedMemorys are no longer referenced, shouldn't be found here.
- println of error changed to failed

* Loading memories from files
- Many changes based on review
- move stuff into experimental
- clean up annotation manipulation
- manage tests better
- use more standard practices for transform

* Loading memories from files
- More review changes
- Move doc from annotation to the object apply method that generates the annotation
- Make scalastyle directives more specific
- Use more efficient collect to generate name to module map
- Made lines obey style length limit
- a couple of cleanups of imports in tests
- removed some commented out code
- optimized checking for lines using .exists
- use _ for unused variable in match

(cherry picked from commit a5185d2c)

master 4cccd877

# Conflicts:
#	build.sbt

(cherry picked from commit 1fd9957b)

(cherry picked from commit 4de6848e)

(cherry picked from commit b6b00a93)

(cherry picked from commit b72f5b8a)

Add support for Input() and Output() (available in Chisel2 since ucb-bar/chisel2-deprecated#734) and test for same.

(cherry picked from commit 8f96e509)

Documentation for example had parameters in wrong order, and was missing @param. Additionally, it was lacking a module wrapper. This has been corrected.

(cherry picked from commit e564fff1)

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
(cherry picked from commit 55c98cbb)

Resolves #841

(cherry picked from commit b17998ea)

(cherry picked from commit b545a4e0)

They should not be deprecated until zero-width wires actually work

(cherry picked from commit 94be48d7)

(cherry picked from commit 9591d690)

(cherry picked from commit 1fd9957b)

This reverts commit d0cdd3b4.

Fixes #763
Add tests for #763 and #472

This has a few implications
* Constructing a literal no longer increments _T_ suffixes
* Internally, wrapping a literal Bits in Node(...) will work
* Literal Bools work in withReset/withClockAndReset