Previously, a view of an empty Record or Vec would always have a
litValue of 0.

Also tweak Vec.Lit code to use cloneAsSuperType rather than implementing
its own version of the same concept.

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Co-authored-by: chiselbot <chiselbot@users.noreply.github.com>

While these tests pass, they generate invalid FIRRTL
that firtool would reject.  Rewrite without using input probes.

* type equivalence includes probe
* Add type equivalence checks for Probes, including writeability and color.

* scalatest: 3.2.14 => 3.2.18
* scalacheck-1-16:3.2.14.0 => scalacheck-1-18:3.2.18.0
* json4s-native: 4.0.6 => 4.0.7
* commons-text: 1.10.0 => 1.12.0
* os-lib: 0.9.1 => 0.10.0
* upickle: 3.1.0 => 3.3.0

* Delete moultingyaml, it has been unused for a long time
* Make Mill versions consistent with SBT versions

It should never have been a public API

Tiny cleanup of the test once the name of the function changed

The DataMirror API allows users who know what they're doing to access a module's ports before it is closed.

This is an automated commit generated by the `circt/update-circt` GitHub
Action.

Co-authored-by: chiselbot <chiselbot@users.noreply.github.com>

* minimal reproduce Nested Instantiate bug

* expose cache and elaborated defination to inner defination

* fix up

Restore #3912 and #3825.
Use intrinsic expression instead of intrinsic module.

This reverts commit 347d82b8.

* implement the instantiable SerializableModule

* add test

* SizeOf: Use intrinsic expression instead of IntrinsicModule.
* mux2cell, mux4cell: Use intrinsic expression.
* isX: use intrinsic expression.
* PlusArgsValue: use intrinsic expression
* PlusArgsTest: IntrinsicExpr, drop unused type argument.  Preserve old interface but mark deprecated.
* clock gate: use intrinsic expression.
* tests: split out FIRRTL generation test from compile check.