Make mergify open backport PRs & signal on failed cherry-picks

Overriding will always result in a NullPointerException

Introduces mutually-exclusive traits RequireAsyncReset and
RequireSyncReset to set the type of the implicit reset in
MultiIOModules. The Scala-type remains Reset, but the Chisel
elaboration-time checks apply.

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

Co-Authored-By: Albert Magyar <albert.magyar@gmail.com>

Co-Authored-By: Albert Magyar <albert.magyar@gmail.com>

* Clean up aspects

* Refactored InjectingAspect with InjectorAspect

* Made AspectLibrary work with objects

* Cleaned up code

* Apply suggestions from code review

* Added tests, removed deprecated newInstance call

* Backed out removal of newInstance as exceptions were different

* Removed trailing commas

The release process uses python to scan and set expected versions for a release. The `val defaultVersions = ` stanza should be present for this to work.

Migrate to Dependency Wrapper

This changes Phase dependency specification to use the new Dependency
wrapper. Previously, dependencies were specified as classes.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

* Remove CCC Upcoming Event

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

* Add developer meetings as upcoming events

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

* add mill build
* add gitignore and mill version

Co-authored-by: Schuyler Eldridge <schuyler.eldridge@gmail.com>

Close #1134

Co-authored-by: Megan Wachs <megan@sifive.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

Emit FIRRTL andr, orr for Bits.{andR, orR}

Change the emission strategy for Bits methods andR and orR to emit
FIRRTL bitwise reduce operations andr and orr.

Add two tests that assert the correct behavior of these operations in
BitwiseOpsSpec.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

Adds additional Scaldoc to the RegNext object that (1) indicates that
the width is not set and (2) shows an example of how to construct a
RegNext-like construct with a set width.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

* Add support for readUnderWrite to SyncReadMem

* Add write collision behavior test to MemorySpec

* Update constant names

Add method asBool to Clock.

Co-authored-by: Jim Lawson <ucbjrl@berkeley.edu>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

* Remove redundancy code

* Remove blank line

* BitPat supports whitespace and underscores, presumably for human readability.
The BitPat.parse factory though did not remove these from the returned count.
This fixes that adds whitespace and underscores to the unit tests
This is an updated vesion of Chisel PR #1069

Co-authored-by: Chick Markley <chick@qrhino.com>
Co-authored-by: Jim Lawson <ucbjrl@berkeley.edu>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

Provides Double and BigDecimal methods to  access literal values for FixedPoint and Interval

Co-authored-by: Chick Markley <chick@qrhino.com>

* Change when thunks return type to Any

Changes the type of the thunk for when and WhenContext methods from
call-by-name Unit to call-by-name Any. This prevents a
warning (-Ywarn-value-discard) where a when thunk is returning
something other than Unit that is then discarded, e.g., another
WhenContext.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

* Change switch thunk return to type to Any

Changes the type of switch thunks from call-by-name Unit to
call-by-name Any. This prevents a warning (-Ywarn-value-discard) when
the internals of a switch block return something other than Unit which
is then discarded.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

# Conflicts:
#	src/test/scala/chiselTests/IntervalSpec.scala