* implement the instantiable SerializableModule

* add test

* SizeOf: Use intrinsic expression instead of IntrinsicModule.
* mux2cell, mux4cell: Use intrinsic expression.
* isX: use intrinsic expression.
* PlusArgsValue: use intrinsic expression
* PlusArgsTest: IntrinsicExpr, drop unused type argument.  Preserve old interface but mark deprecated.
* clock gate: use intrinsic expression.
* tests: split out FIRRTL generation test from compile check.

* [binder] Support constructing integers larger than 64 bits
* [cd] Bump CIRCT from firtool-1.72.0 to firtool-1.73.0
* mill format

Co-authored-by: Asuna <SpriteOvO@gmail.com>
Co-authored-by: chiselbot <chiselbot@users.noreply.github.com>
Co-authored-by: Will Dietz <will.dietz@sifive.com>

This follows up on https://github.com/chipsalliance/chisel/pull/3960
to address the behavior at the final module for the sink being
driven. We already have special handling for boring out from the
original source, and we need the inverse here. When we reach the final
sink, if it is an input port, we should use it, rather than boring
into the module and connecting to it.

* bump nix flake.lock

* Add integration test for PanamaConverter

* reformat lit, panama libraries
* reformat sc files
* use mill to check format
* use setup-java@v4 for CI
* Add license to Benchmark.scala and run Scalafmt on benchmark module
* Update CONTRIBUTING with new mill scalafmt instructions

---------

Co-authored-by: Jack Koenig <koenig@sifive.com>

Optimize truth table merge

Most TruthTables have a default of all dont care. We can optimize this
common case by doing actual work in TruthTable.split and
TruthTable.merge.

The user can override this method to customize how their Data
applies waive, squeeze, and exclude in its Connectable.

This allows it to test package private methods.

- Changed TraceStyle.Vcd to include a trace file name
- Added OptimizationStyle.OptimizeForSimulationSpeed and associated Verilator flags
- Added a sys.addShutdownHook to kill the simulation process in case of
  Ctrl+C etc. Tested on MacOS only. Seems to be _mostly_ working, so
  probably better than nothing.

Fix a bug where a layer definition would only be added to Builder state if
it was used in a layer block.  Also add these layers to the Builder state
if they are used by a layer-colored probe type or by a module's enable
layer.

Fixes #3983.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Previously, the function would infinitely recurse resulting in a stack
overflow.

* Update firtool emission option for verification flavors
* [binder] Support constructing integers larger than 64 bits
* [cd] Bump CIRCT from firtool-1.71.0 to firtool-1.72.0

Co-authored-by: Asuna <SpriteOvO@gmail.com>
Co-authored-by: chiselbot <chiselbot@users.noreply.github.com>

This API allows users to bore to a sink they plan to drive, which complements the existing API to bore from a source to read.

* Specify right convention for modules

* Specify `desiredName` as `defname` for `extmodule`

Make Workspace parametric: allow running a simulation in ChiselSim with different firtool options i.e. -g (#3932)

This is an automated commit generated by the `circt/update-circt` GitHub
Action.

Co-authored-by: chiselbot <chiselbot@users.noreply.github.com>

Co-authored-by: Jack Koenig <koenig@sifive.com>

The website build has started failing for an unknown reason, but there
was a warning about the Algolia integration and bumping Docusaurus seems
to fix the issue. Docusaurus 3.1.1 introduces checks for broken anchors
which is also fixed in this PR. One of the broken anchors was to a
section on FixedPoint, as FixedPoint was removed, this section was
deleted.

IntrinsicModules (intmodule's in FIRRTL) have replaced this entirely
for some time now.

* Fix integration test for PanamaProperty

* Move to `toString` following #3940