- Mar 03, 2023
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chick authored
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chick authored
from chisel3.util
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Jack Koenig authored
* Change artifact to org.chipsalliance::chisel:5.0-SNAPSHOT * Fix website to point to renamed repo (chisel) * Add "unipublish" for single artifact publishing It is a new pseduo-project in the SBT build that aggregates build artifacts from the real projects into a single artifact. It must now be used for publishing and MiMa binary compatibility checking. There are also other changes needed for publishing under org.chipsalliance, namely we have to publish to a different sonatype snapshots repository: https://s01.oss.sonatype.org/
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- Mar 01, 2023
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Jack Koenig authored
[chisel5] Remove SFC Compiler from FIRRTL Subtree
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Schuyler Eldridge authored
Fix all FIRRTL Scaladoc warnings and re-enable fatal warnings when building the docs. Signed-off-by:Schuyler Eldridge <schuyler.eldridge@sifive.com>
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Schuyler Eldridge authored
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Schuyler Eldridge authored
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Schuyler Eldridge authored
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Schuyler Eldridge authored
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Schuyler Eldridge authored
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Schuyler Eldridge authored
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Schuyler Eldridge authored
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Schuyler Eldridge authored
Fix all FIRRTL compile warnings and enable fatal warnings for FIRRTL compilation. Signed-off-by: -
Schuyler Eldridge authored
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Schuyler Eldridge authored
FIRRTL hasn't had custom logging since it was removed in 3e626e39 . Remove a resource that was missed in this original purge. Signed-off-by:
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Schuyler Eldridge authored
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Schuyler Eldridge authored
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Schuyler Eldridge authored
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Schuyler Eldridge authored
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Schuyler Eldridge authored
Remove infrastructure related to constraint solving and vestigial infrastructure related to interval types. Signed-off-by: -
Schuyler Eldridge authored
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Schuyler Eldridge authored
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Schuyler Eldridge authored
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Schuyler Eldridge authored
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Schuyler Eldridge authored
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Schuyler Eldridge authored
Remove RunFirrtlTransform and RunFirrtlTransformAnnotation. This is preparatory work from removing Transform. Signed-off-by: -
Schuyler Eldridge authored
Rip out unused things from Emitter.scala. Move the AddImplicitOutputFile phase from firrtl to circt and update this to do the right thing with a SplitVerilog annotation. Signed-off-by: -
Schuyler Eldridge authored
Remove the FIRRTL backend. This does not remove FIRRTL serialization, just the SFC Transforms that create EmittedFirrtlModule annotations. A FIRRTL circuit can still be serialized to text in the normal way. Signed-off-by: -
Schuyler Eldridge authored
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Schuyler Eldridge authored
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Schuyler Eldridge authored
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Schuyler Eldridge authored
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Schuyler Eldridge authored
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Schuyler Eldridge authored
Remove everything from WIR.scala (Working IR) which is not actually IR. I.e., this removes everything except CHIRRTL constructs and Kind/Flow. A method is moved into CheckTypes that is used by Chisel to determine connection validity. This was unnecessarily bouncing through WrappedType when it can be simplified to not do the boxing. Signed-off-by: -
Schuyler Eldridge authored
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Schuyler Eldridge authored
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Schuyler Eldridge authored
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Schuyler Eldridge authored
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Schuyler Eldridge authored
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Schuyler Eldridge authored
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