A better solution might be to address the "point of failure" - the removal of forceName in UserModule.scala

They should not be deprecated until zero-width wires actually work

binding => topBinding so that partial Bundles work and undefined Bundle members properly forward to DontCareBinding

This shows errors comparing literals

Provide direct conversion from ChiselIR to FIRRTL.
Provide Driver support for dumping ProtoBuf.

Resolves #841

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

Documentation for example had parameters in wrong order, and was missing @param. Additionally, it was lacking a module wrapper. This has been corrected.

Add chisel3.experimental.IO for programmatic port creation in Raw and
MultiIOModules. suggestName is required to name ports that cannot be
named by reflection. Two ports cannot be given the same name.

Fixes #763
Add tests for #763 and #472

This has a few implications
* Constructing a literal no longer increments _T_ suffixes
* Internally, wrapping a literal Bits in Node(...) will work
* Literal Bools work in withReset/withClockAndReset

The Vec constructor invokes the gen argument for each element in the
Vec. Since VecInit invokes cloneSupertype which touches every element of
the input Seq, this was an n^2 operation. Vec.apply accepts its
arguments by value so cloneSupertype is only called once. It then calls
cloneType on that once for each element in the Vec, which is constant
time reducing the overall complexity of VecInit to just n.