Use bulkConnect in Vec,fill if any (flattened) element of the Vec has a direction associated with it.
This impetus for this came out of discussion during the chisel meeting of 8/24/16 in response to errors running the chisel tutorial examples Adder test.

Input, Output, and Flipped clone their inputs.

As a side-effect, handle BlackBoxes correctly.

Revive support for firrtl flip direction.
Remove compileOptions.internalConnectionToInputOk

Assume LHSItOutput if neither side is driving.
Restore Wire()'s removal of direction in binding.

* Make "def width" a private API; expose isWidthKnown instead

Resolves #256.

Since width was used to determine whether getWidth would succeed, I added

    def isWidthKnown: Boolean

but another option would be to expose something like

    def widthOption: Option[Int]

...thoughts?

* Document getWidth/isWidthKnown

* Add widthOption for more idiomatic Scala manipulation of widths

Nothing uses these now, but when we integrate Stephen's PR200, we'll need a way to selectively enable some strict connection checks on a file by file basis. We plan to do this using package imports which will define suitable compilation options.

The API allowed this before, but not safely, as users could create
name conflicts.  This exposes the pre-deduplication/sanitization
naming API, and closes the other one.

It's not entirely clear what the FIRRTL implementation supports, so
I'm using the ANSI C requirements for the time being.

This has been deprecated for a long time now (and really shouldn't
have existed to begin with).

Deprecating toBits removes the capability to cast an arbitrary
type to UInt.  While it's still possible to do so using asBits.asUInt,
this creates boilerplate.  (asBits is almost never useful itself.)

Remove .Lit(x) usage.
Undo "private" scope change.
Change "firing" back to "fire".
Add package level NODIR definition.