Commits · f6ea3dc1bb5efb4455fd3b995ced36add85a44c0 · github.com / freechipsproject / chisel3

Jan 26, 2016
- Changed tests to pass with change to postfix of generated name · f6ea3dc1
  azidar authored Jan 25, 2016
  
  f6ea3dc1
- Changed first generated name to use _0 postfix · a637f4f0
  azidar authored Jan 25, 2016
  
  a637f4f0
Jan 25, 2016
- Fixed tests that broke from changing verilog backend and removing mask from write mport declaration · 5cb43f0c
  azidar authored Jan 24, 2016
  
  5cb43f0c
- Made CInfer robust to high firrtl errors · a899ff36
  azidar authored Jan 24, 2016
  
  a899ff36
- Added muxing on passive aggregate types · 8265e2e6
  azidar authored Jan 24, 2016
  
  8265e2e6
- Merge branch 'new-mem' of github.com:ucb-bar/firrtl into new-mem · 63b36684
  azidar authored Jan 24, 2016
  
  63b36684
- Removed hashing as it made refchip slower to compile · 9a957a40
  azidar authored Jan 24, 2016
  
  9a957a40
- Added DefMemory to CInfer Types · 2e1c88ae
  azidar authored Jan 24, 2016
  
  2e1c88ae
Jan 24, 2016
- Fix Verilog syntax errors for print/stop · 559cc89a
  Andrew Waterman authored Jan 23, 2016
  
  559cc89a
- Update rocket regression · 2dd174ce
  Andrew Waterman authored Jan 23, 2016
  
  2dd174ce
- Removed buggy optimization of dshr and dshl · 3d472002
  azidar authored Jan 23, 2016
  
  3d472002
- Moved inst declarations after other declarations · c241ed5e
  azidar authored Jan 23, 2016
  
  c241ed5e
- Fixed commas for instances in verilog · 725a4a4a
  azidar authored Jan 23, 2016
  
  725a4a4a
- Added more semicolons · fd3941ad
  azidar authored Jan 23, 2016
  
  fd3941ad
- Added semicolon after assigns in verilog · 7cc42d48
  azidar authored Jan 23, 2016
  
  7cc42d48
- off by one error when emitting ports in verilog · 6acc9b5c
  azidar authored Jan 23, 2016
  
  6acc9b5c
- Fixed combinational read verilog backend · eb8e4cc2
  azidar authored Jan 23, 2016
  
  eb8e4cc2
- Removed more prints ;) · a4c84651
  azidar authored Jan 23, 2016
  
  a4c84651
- Removed print statements · 7e7063d1
  azidar authored Jan 23, 2016
  
  7e7063d1
- Fixed bug where the write mask wasn't being generated correctly · 4426f118
  azidar authored Jan 23, 2016
  
  4426f118
- Removed debugging printlns · bc8a54c2
  azidar authored Jan 23, 2016
  
  bc8a54c2
- Added inference to mports · d98526e5
  azidar authored Jan 23, 2016
  
  d98526e5
Jan 23, 2016
- Added prefix checker, now compliant with firrtl spec · 854b5d1b
  azidar authored Jan 23, 2016
  
  854b5d1b
- Changed chirrtl to not require known mask values · 99062792
  azidar authored Jan 23, 2016
  
  99062792
- Merge branch 'new-spec' of github.com:ucb-bar/firrtl into new-mem · cce5603a
  azidar authored Jan 22, 2016
```
Conflicts:
	spec/spec.pdf
```
  cce5603a
- Added pdf · 213338b8
  azidar authored Jan 22, 2016
  
  213338b8
- Added a word · c6f01cdb
  azidar authored Jan 22, 2016
  
  c6f01cdb
- Added funding number, as well as additional acknowledgements · 3a3d5da8
  azidar authored Jan 22, 2016
  
  3a3d5da8
Jan 22, 2016
- Finished version 0.2.0. Included leftovers for future user manual. · 9818f221
  azidar authored Jan 22, 2016
  
  9818f221
- First cut, some unfinished sections but readable · 4321cb7e
  azidar authored Jan 21, 2016
  
  4321cb7e
Jan 21, 2016
- WIP, almost finished with expressions. Removed poison, add is invalid and validif() · 21275ed0
  azidar authored Jan 20, 2016
  
  21275ed0
- WIP, need to update chirrtl with new mask syntax · a94299f2
  azidar authored Jan 20, 2016
  
  a94299f2
- WIP: finished partial connect · 9fc446e4
  azidar authored Jan 20, 2016
  
  9fc446e4
Jan 20, 2016
- WIP: Writing new spec. · 1d8bf5d4
  azidar authored Jan 19, 2016
  
  1d8bf5d4
Jan 18, 2016
- Forgot to add the changes · 26355975
  azidar authored Jan 17, 2016
  
  26355975
- Fixed error where memory of size 1 would create an index of size 0. This can... · 6e898b3c
  azidar authored Jan 17, 2016
```
Fixed error where memory of size 1 would create an index of size 0. This can be fixed in the future with a pass that removes these memories
```
  6e898b3c
- Added check for uint on access index type · 0b05d1f7
  azidar authored Jan 17, 2016
  
  0b05d1f7
- Removed temporary files · e19af483
  azidar authored Jan 17, 2016
  
  e19af483
- BIT-AND, BIT-OR, and BIT-XOR now can accept SInts. Fixed tests · 42789876
  azidar authored Jan 17, 2016
  
  42789876
Jan 17, 2016
- Added a bunch of tests and added firrtl-stanza and firrtl-scala to .gitignore · 81e47120
  azidar authored Jan 16, 2016
  
  81e47120