Commits · f4e4ee0e7586797b6a100062e072143977d04fef · github.com / freechipsproject / chisel3

May 14, 2020

Merge pull request #1601 from freechipsproject/speed-up-infer-types · f4e4ee0e
Jack Koenig authored May 13, 2020
```
Speed up InferTypes and CInferTypes
```
f4e4ee0e
Remove a redundant Expression traversal in InferTypes · 26693f72
Jack Koenig authored May 12, 2020

26693f72
Use HashMap instead of LinkedHashMap in InferTypes · a15f65c8
Jack Koenig authored May 12, 2020
```
Do the same in CInferTypes
```
a15f65c8

Update json4s-native to 3.6.8 (#1607) · d6e3cd00

Jim Lawson authored May 13, 2020

Co-authored-by: Scala Steward <me@scala-steward.org>
Co-authored-by: Scala Steward <43047562+scala-steward@users.noreply.github.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

d6e3cd00

Update scalacheck-1-14 to 3.1.1.1 (#1606) · 50a90664

Jim Lawson authored May 13, 2020

50a90664

Merge pull request #1592 from freechipsproject/generalize-keyword-collision-to-name-manipulation · 85284228
Schuyler Eldridge authored May 13, 2020
```
Generalize keyword collision to name manipulation, Add {Lower,Upper}CaseNames Transforms
```
85284228
Add test of {Lower, Upper}CaseNames · 93c078b8
Schuyler Eldridge authored May 11, 2020
```
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
```
93c078b8

Add --change-name-case <lower|upper> option · d3ab7e2d

Schuyler Eldridge authored May 11, 2020



Adds an options to the FIRRTL compiler command line to schedule the
LowerCaseNames and UpperCaseNames transforms.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

d3ab7e2d

Add features.{LowerCaseNames, UpperCaseNames} transforms · c8dcdacf

Schuyler Eldridge authored May 11, 2020



Creates the features package and populates it with two new transforms:
LowerCaseNames and UpperCaseNames. These transforms convert all names
in a FIRRTL circuit to lower case or upper case. This is intended to
help align generated Verilog with the policies of the
company/institution using it.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

squash! Add LowerCaseNames and UpperCaseNames transforms

c8dcdacf

Refactor RemoveKeywordCollisions->ManipulateNames · c534c5ab

Schuyler Eldridge authored May 11, 2020



Generalize the operations of the RemoveKeywordCollisions transform
into a new ManipulateNames transform. The ManipulateNames transform is
an abstract transform for making conditional modifications to
keywords/names in a FIRRTL circuit.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

c534c5ab

[Mergify] Add back backporting to 1.2.x (#1595) · 498b833a

Jack Koenig authored May 13, 2020



Labeling a PR with Milestone 1.2.X now will tell Mergify to backport it
to both 1.2.x and 1.3.x.

Co-authored-by: Albert Magyar <albert.magyar@gmail.com>

498b833a

Update scalatest to 3.1.2 (#1584) · 04732401
Scala Steward authored May 13, 2020
```
Co-authored-by: Jim Lawson <ucbjrl@berkeley.edu>
```
04732401

consolidated wire+assign to just wire, with expression inlined (#1600) · 96fbaf50

Murali Vijayaraghavan authored May 13, 2020



* consolidated wire <type> x; assign x = y; to wire <type> x = y;

* Remove dead code from Emitter.scala

Co-authored-by: Albert Magyar <albert.magyar@gmail.com>

96fbaf50

May 12, 2020
- spec: Ran `aspell` on `spec.tex`. (#1564) · d7631649
  Alberto Gonzalez authored May 11, 2020
```
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
```
  d7631649
- Have AppendInfo use MultiInfo, rather than appending with : (#1580) · 32d814cd
  Adam Izraelevitz authored May 11, 2020
```
* Bugfix - have AppendInfo use MultiInfo, rather than appending with :

* Address reviewer feedback

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
```
  32d814cd
- Merge pull request #1558 from freechipsproject/constant-prop-reduction-ops-1343 · 706fbd7e
  Schuyler Eldridge authored May 11, 2020
```
Constant Prop Reduction Operations of Literals
```
  706fbd7e
- Add andr, orr, xorr literal const prop tests · 7227dba8
  Schuyler Eldridge authored May 03, 2020
```
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
```
  7227dba8
- Add andr, orr, xorr literal constant propagation · 82138c96
  Schuyler Eldridge authored May 03, 2020
```
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
```
  82138c96
May 10, 2020
- Merge pull request #1582 from freechipsproject/speed-up-check-high-form · 73c50209
  Jack Koenig authored May 09, 2020
```
Speed up CheckHighForm
```
  73c50209
May 09, 2020
- Don't check Types of Expressions in CheckHighFormLike · 6910d3fb
  Jack Koenig authored May 08, 2020
```
Expression Types are derived. They cannot cause the errors detected by
CheckHighFormLike independently of the user-specified types that remain
chedked. This speeds up CheckChirrtl and CheckHighForm substantially.
```
  6910d3fb
- Lazily generate more detailed error messages in CheckHighFormLike · 8576a68e
  Jack Koenig authored May 08, 2020
```
Don't serialize Expressions unless there is an error
```
  8576a68e
- Make benchmark_cold_compile.py work even if it can't fetch (#1579) · ba03e2f6
  Jack Koenig authored May 08, 2020
  
  ba03e2f6
- deprecating BackendCompilationUtilities trait for object (#1575) · 72c48bbf
  Deborah Soung authored May 08, 2020
  
  72c48bbf
May 07, 2020

Update Travis cache for SBT 1.3 (#1573) · bed5e2d3
Jack Koenig authored May 06, 2020
```
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
```
bed5e2d3
Add parse_firrtl_transform_log utility script (#1543) · 9bc953ca
Jack Koenig authored May 06, 2020
```
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
```
9bc953ca
Merge pull request #1565 from freechipsproject/spec-indent · fd454df0
Schuyler Eldridge authored May 06, 2020
```
Clarify spec definition of indentation and when/else indentation
```
fd454df0
Update spec.pdf · bb6b30e4
Schuyler Eldridge authored May 06, 2020
```
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
```
bb6b30e4
Clarify spec indentation of when/else · 21cf4cfa
Schuyler Eldridge authored May 06, 2020
```
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
```
21cf4cfa

Clarify indentation in spec · 6e572144

Schuyler Eldridge authored May 06, 2020



Co-authored-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Co-authored-by: Albert Magyar <albert.magyar@gmail.com>
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

6e572144

Update sbt-scalafix to 0.9.15 (#1536) · 457bf635

Scala Steward authored May 06, 2020



Co-authored-by: Jim Lawson <ucbjrl@berkeley.edu>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

457bf635

Update sbt to 1.3.10 (#1529) · 1b2be390

Scala Steward authored May 06, 2020



Co-authored-by: Jim Lawson <ucbjrl@berkeley.edu>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

1b2be390

Update moultingyaml to 0.4.2 (#1480) · ee153215

Scala Steward authored May 06, 2020



Co-authored-by: Jim Lawson <ucbjrl@berkeley.edu>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

ee153215

Update protoc-jar to 3.11.4 (#1434) · fc0ea33f

Scala Steward authored May 06, 2020



Co-authored-by: Albert Magyar <albert.magyar@gmail.com>
Co-authored-by: Jim Lawson <ucbjrl@berkeley.edu>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

fc0ea33f

Update scalatest to 3.1.1 (#1405) · 724f8c5b

Scala Steward authored May 06, 2020



* Update scalatest to 3.1.1

* Update scalatest to 3.1.1

* Update scalatest to 3.1.1

Co-authored-by: Jim Lawson <ucbjrl@berkeley.edu>
Co-authored-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

724f8c5b

May 06, 2020

before/after initial block macros (#1550) · e9073463

Deborah Soung authored May 05, 2020



* adding init macros

* fix missing tick

* adding more documentation; fixing up emitter tests

* adding initial-guarding macro test

* prefixing macros with FIRRTL

* cleanup

* typo fix

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

e9073463

May 05, 2020
- add Firrtl plugin info for intellij platform (#1547) · c9d49aa8
  XinJun Ma authored May 05, 2020
  
  c9d49aa8
- Merge pull request #1556 from freechipsproject/legalize-andreduce · 0e8e1296
  Schuyler Eldridge authored May 04, 2020
```
Add LegalizeAndReductionsTransform
```
  0e8e1296
- Add LegalizeAndReductionsTransform · 96241211
  Jack Koenig authored May 01, 2020
```
Workaround for https://github.com/verilator/verilator #2300
present in Verilator versions v4.026 - v4.032. This transform turns AND
reductions for expressions > 64-bits into an equality check with all
ones. It is included as a prerequisite for all Verilog emitters.
```
  96241211
May 02, 2020

Add missing invalidations to some transforms (#1541) · ee0d4079

Schuyler Eldridge authored May 01, 2020



This adds missing invalidations to four transforms:

  - ExpandConnects
  - RemoveAccesses
  - SplitExpressions
  - VerilogMemDelays

This necessarily updates test cases which expect exact transform
orders to reflect the new order.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

ee0d4079

May 01, 2020

Emitter: guard _RAND_* declarations with ifdef (#1548) · 3b4e691b

Albert Chen authored Apr 30, 2020



* Emitter: add declare functions ifdef guard

* Emitter: add ifdef initials

* Emitter: add comments, cleanup

* Emitter: changes from code review

- make new methods private
- use .withDefault
- remove empty initial block

Co-authored-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

3b4e691b