Fixed SlowDecoupledAdder

the lastest refactoring of the decoupled tester, this version groups the events by their controlling device, this make the code a little cleaner and made it easier to manage the handling of the valid alternative

Add a do_flip parameterto DecoupledIO that DeqIO can use instead of inplace flip

Add '=/=' to bits, which does the same as '!='

It looks like this is in Chisel2 now, and some stuff in uncore is using it.
IIRC, we decided that this was the correct thing to do for some Scala style
reasons.

almost there, cannot set the input.valid port to true, any attempt to do so seems to create a verilator does not converge

Now entering type hell!

"Shouldn't be here" when running DecoupledAdderTester

Fixed GCD to work like tutorial
Added exerciser example to Adder in unit_tests

would be nice to have some of this verbosity controlled by a parameter file.
Ability lacking in firrtl printf to control column width makes displays much uglier

Seems like I now have a quirkly but basic system that gather all the port names (even if deeply nested) in to a Map

Meaningful error when resource copy fails.
Seems like this is exposing some deeper error with sbt and external libraries/jars.  Sometimes this error message makes sometimes the entire JVM and sbt dump with SEG fault, I don't think this is a chisel problem