Fix a bug causes incorrect pla generation when input is `?`

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

This introduces a new experimental API for module instantiation that disentagles
elaborating the definition (or implementation) from instantiation of
a given module. This solves Chisel's longstanding reliance on
"Deduplication" for generating Verilog with multiple instances of the
same module.

The new API resides in package chisel3.experimental.hierarchy. Please
see the hierarchy ScalaDoc, documentation, and tests for examples of
use.

Co-authored-by: Jack Koenig <koenig@sifive.com>
Co-authored-by: Megan Wachs <megan@sifive.com>
Co-authored-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Previous incomplete fixes in #2023 and #2031.

The legality of a FIRRTL connection is determined by type and flow.
Chisel does not have access to true flow information. Previous fix
attempts tried to use ActualDirection as a stand-in for flow, but it is
incorrect in many cases. This new approach checks the flows of the
lvalue and rvalues in the connect and flips the connection if either
the lvalue cannot be a sink or the rvalue cannot be a source.

* add Y and N to BitPat.

* add ## for BitPat.

* add rawString API.

* use rawString in decoder

* add select and slice to BitPat.

* replace custom model checker with chiseltest formal verify command

* integration-tests can make use of chiseltest

This is a compromise solution to avoid issues
with binary compatibility breaking changes in chisel3.

* ci: move integration tests into separate job

* run integration tests only for one scala version

* ci: install espresso for integration tests

* Update build.sbt

Co-authored-by: Jack Koenig <jack.koenig3@gmail.com>

Co-authored-by: Jack Koenig <jack.koenig3@gmail.com>

Lazy .fir Emission

This will be slightly slower as it involves converting from Chisel
modules to FIRRTL modules before turning them into Strings. This cost is
somewhat mitigated by doing that conversion lazily such that we never
materialize the entire firrtl Circuit in memory, only 1 module at a
time.

Co-authored-by: Jack Koenig <koenig@sifive.com>

There might be some "@"?

Z3 CI debug

This reverts commit 1e7829eb.

This reverts commit ed894c61.

* [docs] Add example of stripping directions from type

* Apply suggestions from code review

Co-authored-by: Megan Wachs <megan@sifive.com>

* Improve := comment

Co-authored-by: Megan Wachs <megan@sifive.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

* remove DefRegInit, change DefReg API with option defination.

* add error message

* use Option[RegInitIR].

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

Update sbt-scalafix to 0.9.30

DataView is a mechanism for "viewing" Scala objects as a subtype of
`Data`. Often, this is useful for viewing one subtype of `Data`, as
another. One can think about a DataView as a cross between a
customizable cast and an untagged union.

A DataView has a Target type `T`, and a View type `V`. DataView requires
that an implementation of `DataProduct` is available for Target types.
DataProduct is a type class that provides a way to iterate on `Data`
children of objects of implementing types.

If a DataView is provided for a type T to a type V, then the function
.viewAs[V] (of type T => V) is available. The object (of type T) returned
by .viewAs is called a "View" and can be used as both an rvalue and an
lvalue. Unlike when using an .asTypeOf cast, connecting to a "View" will
connect to the associated field or fields of the underlying Target.

DataView also enables .viewAsSupertype which is available for viewing
Bundles as a parent Bundle type. It is similar to .viewAs but requires
a prototype object of the Target type which will be cloned in order to
create the returned View. .viewAsSupertype maps between the
corresponding fields of the parent and child Bundle types.

Pass truth table to espresso using stdin instead of temp file

* Small changes to memory doc
- Fixed typo "except" => "accept"
- Use `Counter` explicitly in ROM section example.

* Fix counter doc compile error

* remove invisible doc block in memory example

* more small fixes to make mem example pass doc compile

* Get rid of sine wave iterator in memory doc

* get rid of tabs on VecInit example

* get rid of tabs on VecInit example

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>