* Add Protocol Buffer emission export

This adds infrastructure and annotations that let a user emit a FIRRTL
circuit as a Protocol Buffer.

Fixes #1696.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

* fixup! Add Protocol Buffer emission export

* make PresetRegAnnotation public

this annotation is useful outside the firrtl compiler:
- to implement a pass that creates registers which
  need to be initialized at the beginning of simulation
  (e.g., for formal verification)
- to support preset registers in treadle

* add PresetRegAnnotation test and deal with annotation correctly in RemoveReset pass

Add a compiler/emitter that can target minimal high form.  This will
produce output that only has CHIRRTL constructs removed.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Remove java.io in MustDedup

Requested by reviewer.

Remove java.io in FileUtils

Update os-lib to 0.7.8

Co-authored-by: Jiuyang Liu <liu@jiuyang.me>

Update sbt-scalafix to 0.9.29

* ReplaceMemMacros: add target rename test case

* ReplaceMemMacros: rename references to instances

* fix renaming for deduped mems

* use grouped DummyAnnos to preserve order

* Apply suggestions from code review

Co-authored-by: Jack Koenig <koenig@sifive.com>

* run scalafmt

* flatten targets

Co-authored-by: Jack Koenig <koenig@sifive.com>

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

Update sbt-scalafix to 0.9.28

Update sbt-mima-plugin to 0.9.2

* Add GenVerilogMemBehaviorModelAnno & vlsiMemGen

* Add CLI support for GenVerilogMemBehaviorModelAnno

* Add simple test for GenVerilogMemBehaviorModelAnno

* Fix for review

1. rename case class Port(prefix, `type`) to Port(prefix, portType)
2. fix AnnotatedMemoriesAnnotation collect function.
3. fix bug that ModuleName is not correct.

* Format DumpMemoryAnnotations & ReplSeqMemTests

* Fix for review

1. Inline genDecl, genPortSpec, genSequential, genCombinational
2. Add DefAnnotatedMemory informations in header
3. Change helpText
4. Check output Verilog by Verilator, the code is from FirrtlRunners#lintVerilog

* Fix ReadWritePort mask name

Co-authored-by: Jiuyang Liu <liu@jiuyang.me>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

* add more inline renaming test cases

* InlineInstances: fix renaming for local targets

* run scalafmt

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

LowerTypes creates a lot of mappings for the RenameMap. The built-in
.distinct of renames becomes a performance program for designs with
deeply nested Aggregates. Because LowerTypes does not create duplicate
renames, it can safely eschew the safety of using .distinct via a
private internal API.

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

* add os-lib to dependency.

* use os-lib in Z3ModelChecker

* fix for review by Kevin.

This function will safely wrap any unserializeable annotations in
UnserializeableAnnotations so that they can be safely serialized to JSON
for logging.

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

* Implement MFC-style source locator compression

* Fix formatting issues

* Fix emitting empty FileInfo if the firrtl doesn't have one

* Remove '.scala' requirement in FileInfo parsing regex

* Handle parsing of FileInfos with no line/col nums

* Split FileInfos only if they match

This should fix any issues with FileInfos that do not use the "file line:col"
format, and allow any valid firrtl using these info comments to compile.

* Add unit tests for locator compression

* Move InfoTests to InfoSpec class

* Fix existing unit tests with fileinfo comments

* Add unit tests to ignore the algorithm's own output