Since the argument is at least 2, this change has no semantic effect.

Both should be zero-width wires.

Provide a better error message when length < 0.

Change log2Up in log2Ceil, which has no effect, since the argument
is always at least 2.

It always should throw an exception when n < 0, but in the specific
case of x.isWidthKnown && x.getWidth == 1, it failed to do so.

This commit also changes log2Up in log2Ceil, which has no effect,
since the argument is always at least 2.

* Use test_run_dir for more tests.

* Use official option and DRY.

Make "test_run_dir" the default for ChiselSpec.
Verify output files are created in DriverSpec tests.

This is necessary for user-defined Record-derived types to retain
the same signal name as they would using a Vec.

Fixes #501. Also added UIntOps test.

Test for ucb-bar/firrtl#407

This turned up after updating #494 (Remove explicit import of NotStrict) and adding the missing implicit CompileOptions to ":="'s signature at which point Scala pointed out FixedPoint's ":=" could not override Data's final ":=" with the same signature: the implicit time bomb.

* Bugfix #513. Needs better test case

* Improved test

* change builder for bundle reflection fix

* fixed bug -- should be not assignable

* Add scaladoc examples for Vec and Bundle

* address comments, added @example tag
eliminate extraneous context

* address comments, added @example tag
eliminate extraneous context

* ok, I've wrestled with the javadoc sytnax, the following commit, is my best result so far

withClockAndReset, withReset, and withClock allow changing the implicit clock and reset.
Module.clock and Module.reset provide access to the current implicit clock and reset.

* Don't allow analog to analog monoconnect
adjust tests accordingly

* demonstrate bit loss in shift right for fixed point

* cleaned up some stuff.
this does not test clean due to bug in firrtl

Used for stitching Verilog inout through Chisel Modules (from BlackBox
to BlackBox)

There was some dubious (certainly unclear) code organization in the CompatibiltySpec tests. The isPow2() test was randomly failing in Jenkins builds. This may address the problem.

* Fix up Absolute value #abs
Defines #abs in Num
Implement #abs in UInt
Change #abs in SInt to return an SInt
Change #abs in FixedPoint to return a FixedPoint
Added  a couple of tests
Add some scala style suppression to Bits so I can read code in IntelliJ

* Per review
Add tests that abs works for positive values
Added SInt and UInt tests for abs to new underpopulated IntegerMathSpec
Used fixed point literals in fixed points abs definition

Retain un-deprecated SeqMem in compatibility mode, deprecate in chisel3.

* Added vec IO tests for #104

* Added Vec test case for Reg of vecs

* Change Vec creation to check if gen is lit (and hence needs to be declared)
Fixes #104

* Fix tests (add IO())), Vec.fill()

* Fix deprecated usage.

* Add Binding IO() NPE fix so tests pass.

* Fix style - use space consistently.

* Fix style - use space consistently.

* Move to cookbook
* Change FSM implementation to use switch & is
* Add non-FSM implementation
* Add execution-driven test

* Move copyResourceToFile() to BackendCompilationUtilities.
* Move BackendCompilationUtilities into a firrtl util package.
Some of this could be moved into a more general tools package, but since chisel3 already has a dependency on firrtl ...
* Push util down into firrtl so as not to conflict with scala.util.
* Use new createTestDirectory. Fixes #452.