This reverts commit 3c8a810e.

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

Also delete an errant println in InstanceSpec

Chisel <> semantics differ somewhat from FIRRTL <= semantics,
so we only emit <= when it would be legal. Otherwise we continue
the old behavior of emitting a connection for every leaf-level
Element.

Co-authored-by: Deborah Soung <debs@sifive.com>
Co-authored-by: Jack Koenig <koenig@sifive.com>

Co-authored-by: Jiuyang Liu <liu@jiuyang.me>
Co-authored-by: Megan Wachs <megan@sifive.com>
Co-authored-by: Jack Koenig <koenig@sifive.com>

* Tweaks to the Verilog-vs-Chisel Page

* Update cookbook.md

* Update verilog-vs-chisel.md

* Update verilog-vs-chisel.md

* Issue errors on out-of-range extracts when width is known

Firrtl will catch this later on, but better to error early if possible.

* Test that errors are generated on OOB extracts when width is known

Co-authored-by: Shola Ogunkelu @Shorla
Co-authored-by: Megan Wachs <megan@sifive.com>
Co-authored-by: Deborah Soung <debs@sifive.com>

Completed as part of Outreachy Internship Dec 2021-March 2022.