Verilator 5.0 emits C++ which requires "-std=c++11".  This is normally
handled by the Verilator configure script.  However, since Chisel
doesn't use this, the lack of this when running with Verilator 5.0 can
result in compilation failures in tests.  Add this flag so that
Verilator 5.0 works.  I have not tested this with earlier Verilator
versions.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

* Refactor Shell into BareShell and Shell

Refactor firrtl.options.Shell into BareShell and Shell.  This is done to
enable the leaner BareShell to _not_ provide no command line options
other than "--help".  This enables use cases like the ChiselStage$
object which should not have options that are available to a Shell,
e.g., "--target-directory".

* Use BareShell in ChiselStage$ options (remove -td)

Change the ChiselStage$ object to use BareShell which enables this to
now reject options like "--target-directory"/"-td" which have no
effect.  Add a test that "-td" is rejected by emitCHIRRTL.

---------

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

* Add test for new error message on litValue on Bundle containing DontCare
* Refactored so litValue errors when bundle has DontCare elements
  But that litOption does not error when bundle has DontCare elements

Co-authored-by: Jack Koenig <koenig@sifive.com>

Pushes to main will now have SNAPSHOTs based on `git describe --tag`.
Also run CI workflow (which includes publishing) on push to any tag and
enable workflow_dispatch.

Create deprecated alias in package chisel3.util.

Move LFSRSpec, QueueSpec, and QueueFlushSpec to integrationTests for
some CI parallelism.

Update Mergify config and add generation script to this repository

Also slight quality-of-life improvement to comments in the template.

Updated for new main branch and 3.6.x.
Generated with .github/mergify/gen-config.sc

Derived from original Ammonite script:
https://github.com/ucb-bar/chisel-repo-tools/blob/d3432790d746a3e3643acc843377f0d82b830466/scripts/mergify.sc

* Change artifact to org.chipsalliance::chisel:5.0-SNAPSHOT
* Fix website to point to renamed repo (chisel)
* Add "unipublish" for single artifact publishing

It is a new pseduo-project in the SBT build that aggregates build
artifacts from the real projects into a single artifact. It must now be
used for publishing and MiMa binary compatibility checking.

There are also other changes needed for publishing under
org.chipsalliance, namely we have to publish to a different sonatype
snapshots repository: https://s01.oss.sonatype.org/

[chisel5] Remove SFC Compiler from FIRRTL Subtree

Fix all FIRRTL Scaladoc warnings and re-enable fatal warnings when
building the docs.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Fix all FIRRTL compile warnings and enable fatal warnings for FIRRTL
compilation.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

FIRRTL hasn't had custom logging since it was removed in
3e626e39

.  Remove a resource that was missed in
this original purge.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Remove infrastructure related to constraint solving and vestigial
infrastructure related to interval types.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Remove RunFirrtlTransform and RunFirrtlTransformAnnotation.  This is
preparatory work from removing Transform.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Rip out unused things from Emitter.scala.  Move the
AddImplicitOutputFile phase from firrtl to circt and update this to do
the right thing with a SplitVerilog annotation.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Remove the FIRRTL backend.  This does not remove FIRRTL serialization,
just the SFC Transforms that create EmittedFirrtlModule annotations.  A
FIRRTL circuit can still be serialized to text in the normal way.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>