* smt: add test for write port collision

* smt: add missing call to insertDummyAssignsForMemoryOutputs

* smt: fix typo in write port code

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

* split big Emitter to submodules.

* fix all deprecated warning.

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

* smt: add tests for assert name clashes

* smt: ensure unique signal names with a namespace

this fixes issues #1934

Fix verilog prep

* Make Stage.run protected

Change the access modifier of Stage.run from no modifier to protected.
This method is really an internal API that the user implements with
the main entry point for a Stage being "execute" or "transform". By
allowing users to access "run" they can bypass checks, mandatory file
reads/writes, and wrappers.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

* Make FirrtlStage.run protected

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Fix "fix" for negative literals > 32 bits

Overflow of 32-bit Int would cause any negative literal value equal to
-(2^(width % 32 - 1)) where width >= 32 to be incorrectly inverted

VerilogMemDelays: fix lowering of direct mem-to-mem connections

* Also clean up VerilogMemDelaySpec structure

Also speed up common case of Array[Byte]

now points to apache 2.0

Both use EliminateTargetPaths to duplicate modules based on annotations.
Currently, EliminateTargetPaths API is a little too limited so it
duplicates more than it should which effectively breaks Dedup whenever
DontTouchAnnotations are present.

Also, make ConstProp and DCE treat all HasDontTouches as local
annotations even if they are instance annotations. This is more
conservative but it is generally better to preserve deduplication than
to maximally optimize every instance.

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

Specify appropriate Chisel and Treadle branches for CI tests

These options are generally specific to a stage and thus should not be
propagating across serialization

* test multiinfo comparison and mux cond inlining

* loosen inlining conditions

* fix typo

* include dshlw

* fix test

Also rename --Wno-scala-version-warning to
--warn:no-scala-version-deprecation and adopt naming convention where
resulting annotation matches the CLI option

Legalize mem port clocks to avoid Verilator-unfriendly sensitivity lists

* InlineBooleanExpressions: test DontTouch

* run scalafmt

Make mill compatiable to 2.13.

Restrict boolean inlining to avoid context-sensitive width bugs