- Oct 02, 2017
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Jack Koenig authored
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Jack authored
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- Oct 01, 2017
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Albert Magyar authored
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Adam Izraelevitz authored
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Adam Izraelevitz authored
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- Sep 30, 2017
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Jack Koenig authored
Defined as the range from ' ' to '~' [0x20, 0x7e]
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Jack Koenig authored
This prevents collisions for one prefix (including temp) from incrementing the suffix for other prefixes. Makes names more stable.
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- Sep 23, 2017
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Jack Koenig authored
Refactor StringLit to use String instead of Array[Byte]
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- Sep 22, 2017
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Edward Wang authored
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Chick Markley authored
When calling verilator in a subdirectory like ./test_run_dir/... verilator will read the verilog file from the current working directory if there is a file there with the right name. This fix specifies the specific path of the verilog file intended.
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- Sep 20, 2017
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Chick Markley authored
not exit when --help is included in program flags
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Chick Markley authored
Adds programArgs to commonOptions programArgs is all arguments on command line with out leading -/+ or are not bound to a flag. Create simple test
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- Sep 15, 2017
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Jim Lawson authored
* Update sbt to 0.13.16; add Scala 2.12 support. To clean, test, and build Scala 2.11 and Scala 2.12 versions: % sbt +clean +test +publishLocal * Update Travis to test in 2.11.11 and 2.12.3 * Try different way of providing Travis Scala version * Attempt to get verilator built before tests.
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- Sep 13, 2017
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Schuyler Eldridge authored
* Make pathsInDAG walk all possible paths Signed-off-by:Schuyler Eldridge <schuyler.eldridge@ibm.com> * Use linearization order when finding all paths in DAG
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- Sep 07, 2017
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Edward Wang authored
Since InstanceGraph now has all modules in its graph, test ConstProp on all modules as a default behaviour. - Need to think about how to target ConstProp only for a specific module? Close #644
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- Sep 06, 2017
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Edward Wang authored
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Albert Magyar authored
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- Sep 01, 2017
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Adam Izraelevitz authored
* Added option to emit final annotations * Removed extra > from output-anno-file * Removed other extra > from input-anno-file
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- Aug 24, 2017
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Adam Izraelevitz authored
* Reorder port and wire assignments in Verilog * Fixed up syntax
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- Aug 15, 2017
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Jack Koenig authored
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- Aug 05, 2017
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Andrey Ayupov authored
bug fix for cases when we want to flatten a module in which a module is instantiated multiple times (#634)
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- Aug 02, 2017
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Donggyu authored
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- Jul 27, 2017
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Andrey Ayupov authored
* initial implementation of InlineDeepTransformation * rewrote transformation to not have any side effects in terms on inlining that was not annotated to be inlined * minor rewrites * renamed transformations to Flatten * fixes according to review * added more comments and fixed formating/style * fixed spacing, minor style fixes
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- Jul 19, 2017
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Jack Koenig authored
Fix ConstProp bug where multiple names would swap with one
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- Jul 18, 2017
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Donggyu Kim authored
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Jack Koenig authored
Fixes issue in https://github.com/freechipsproject/rocket-chip/pull/848
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- Jul 15, 2017
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Jack Koenig authored
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- Jul 07, 2017
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Chick Markley authored
* Fixed inability to disable combo loop check Moved checking of dontCheckComboLoops into loadAnnotations so that it works in cases where Driver.execute is not used. * Fix test for annotations, modifications to loadAnnotations made 2 more annotations visible. * Remove debug println from DriverSpec
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- Jul 04, 2017
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Jack Koenig authored
Const prop regs
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- Jun 30, 2017
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Jack Koenig authored
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Jack Koenig authored
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Jack Koenig authored
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Jack Koenig authored
Preserve "better" names in Constant Propagation
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Jack Koenig authored
Names that do not start with '_' are "better" than those that do
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Jack Koenig authored
Use Travis Build Stages
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Jack authored
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Jack authored
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Jack Koenig authored
Improvements to Constant Propagation and Testing
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- Jun 29, 2017
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Jack Koenig authored
Constant Propagation will not optimize across components marked dontTouch
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Jack Koenig authored
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