* Create a simple generic graphviz renderer for DiGraph
There are three basic kinds
- A simple default renderer
- A ranked renderer that places nodes in columns based on depth from sources
- A sub-graph render for graphs that contain a loop
  - Renders just nodes that are part of first loop found
  - Plus the neighbors of the loop
  - Loop edges are shown in red.

* Create a simple generic graphviz renderer for DiGraph
- Moved the graph loop finder into DiGraph
- Fixed scala doc per Edward's comments

* Run CheckHighForm after all non-emitter transforms in firrtl tests

* Remove shlw from checks.scala

* Removed mistake in fix

* Fix FirrtlSpec fix

Fix almost all scaladoc warnings, add source links

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

This fixes all Scaladoc warnings except for those trying to link to
Java.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

* refactor InferWidths to allow for extra contraints, add InferWidthsWithAnnos

* add test cases

* add ResolvedAnnotationPaths trait to InferWidthsWithAnnos

* remove println

* cleanup tests

* remove extraneous constraints

* use foreachStmt instead of mapStmt

* remove support for aggregates

* fold InferWidthsWithAnnos into InferWidths

* throw exception if ref not found, check for annos before AST walk

Instead, just forward the exception

Previously would require all requested reviewers must have approved a PR before merging.

* No time left for you - quickly rename deep bundles still occasionally fails.
Run the "quick" calibration test three times and choose the maximum as the basis for comparison with the "deep" test.

* Rename local variable to less confusing name.

* Correctly handle dots in loaded memory paths

* Added test for loadmem filename

* Attempt to deal with timing vagaries in UniquifySpec.quicklyrenamedeepbundles
Switching to Scala 2.12.8 cause this test to start failing on OSX. Try earlier scheme to compare shallow vs deep to reduce brittleness.

* Address review concerns; update comment.

Fixes #219

* Adds AsyncResetType (similar to ClockType)
* Registers with reset signal of type AsyncResetType are async reset
  registers
* Registers with async reset can only be reset to literal values
* Add initialization logic for async reset registers

Add "mverilog" Compiler Option, MinimumVerilogEmitter

This uses the foldShiftRight method of the ConstantPropagation
Transform when legalizing Shr PrimOps. This has the effect of removing
literals with bit extracts from the MinimumVerilogCompiler.

This makes the formerly private foldShiftRight method of a public
method of the ConstantPropagation companion object.

Tests in the MimimumVerilogCompilerSpec are updated to check that Shr
is handled as intended.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

This adds the RemoveValidIf Pass to the MinimumLowFirrtlOptimization
Transform. A test case is included to verify that `is invalid` is
properly converted to a connection to zero.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

This adds runs of the minimum Verilog compiler and SystemVerilog
compiler in DriverSpec.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

This adds "mverilog" to the "--compiler" command line option. This
will run the MinimumVerilogCompiler.

This additionally fixes the MinimumVerilogCompiler such that
DeadCodeElimination will not be run (it's not supposed to be). This is
done by adding a MinimumVerilogEmitter, subclassing VerilogVerilog,
that strips the DeadCodeElimination step from its parent.

Additionally, BlackBoxSourceHelper is removed from the
MinimumVerilogCompiler since this will be run by the VerilogEmitter
already.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

* Enhance constant propagation across registers

* Add more elaborate test case for register const prop

This avoids an apparent problem somewhere in sbt and/or scalatest
where the JVM runs out of metaspace if you repeatedly run tasks. This
is an annoyance for FIRRTL developers or users that keep an sbt
session open. This kludges around that by forking all tasks into a
separate JVM.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

* Add memory WRef factory for completeness

* Refactor DefAnnotatedMemory construction for clarity

make more clear for ExecutionOptionsManager log level settings.

* Improve Shl codegen; eliminate Shlw WIR node

If we emit shl(x, k) as {x, k'h0} instead of (x << k), then there's
no need for Verilog-specific padding in the PadWidths pass.  Avoiding
the redundant padding improves compiler/simulator performance and
renders Shlw unnecessary.

* [skip formal checks] Add test

[Top Wiring] Expand top wiring to work on aggregates

* Remove GhpagesPlugin. (#979)

* Restore old SCM reference (after removing ghpages)

* Remove reference to sbt-ghpages plugin.

Constant Propagate dshl and dshr with constant amounts