This adds a prettyPrint method to the DependencyManager to enable
textual visualization of the TransformLikes that a DependencyManager
determines need to be run.

This also cleans up the GraphViz visualization with better edge
coloring and now uses the `name` method when labeling graphviz nodes.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

This makes a change to the Dependency API that breaks chisel3. This
needs to [skip chisel tests], but is fixed with
https://github.com/freechipsproject/chisel3/pull/1270

.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

Add more docs / tests for DiGraph reachableFrom method

This reverts commit eabc3855.

* Revert "Infer resets last connect semantics (#1291)"
* Fix handling of invalidated and undriven components of type Reset
* Run CheckTypes after InferResets
* Make reset inference bidirectional on connect
* Support AsyncResetType in RemoveValidIf
* Fix InferResets for parent constraints on child ports
* Apply suggestions from code review
* Add ScalaDoc to InferResets

Co-authored-by: Albert Magyar <albert.magyar@gmail.com>
Co-authored-by: Schuyler Eldridge <schuyler.eldridge@gmail.com>

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

Constant prop binary PrimOps with matching arguments

* Send in the Yosys

* Add SimplifyBinaryOp trait
* Add extra functionality to comparison folding
* Add tests
* Fix comments from review

Add InstaceGraph (Un)?Reachable Helpers

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

Adds new APIs for querying sets of modules in an InstanceGraph:

  - modules: the set of all modules
  - reachableModules: set of modules reachable from the main/top
  - unreachableModules: set of modules not reachable from the main/top

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

Allow self renames

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

Change the behavior of RenameMap.completeTarget so that self-renames
do not silently *not* happen. Previously, requests to self-rename
would be ignored unless they were packaged in a sequences of renames
that included a self-rename.

Change renames to be recorded distinctly so that multiple requests to
rename to the same thing will now deduplicate. Previously, these
renames would be recorded multiple times. This change was required
because allowing self-renames exposed a bug in InferWidthsAnnosSpec
due to multiple renames.

These changes benefit the situation where you rightly want to do a
self-rename. Namely, when doing module duplication (with the
EliminateTargetPaths transform).

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

Do not record the same rename multiple times

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

* Consume NoDedupMemAnnotations in ResolveMemoryReference

The ComponentName being pointed to by the annotation no longer exists
after ReplaceSeqMems so we should consume the annotations

* Support renaming in ReplaceMemMacros

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

Co-authored-by: Jim Lawson <ucbjrl@berkeley.edu>

Co-authored-by: Jim Lawson <ucbjrl@berkeley.edu>

Include Dead Modules in InstanceGraph.staticInstanceCount

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

Change InstanceGraph.staticInstanceCount to include modules with no
instances. Previously, these modules would just not be included.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

Co-authored-by: Jim Lawson <ucbjrl@berkeley.edu>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

* Generates lint-clean Verilog for the case: x + -1

...where x is anything and 1 is any literal.

Master behavior:

  input x : SInt<8>
  output z : SInt<9>
  z <= add(x, SInt(-2))

generates

  assign z = $signed(x) + -8'sh2;

After this PR:

  assign z = $signed(x) - 8'sh2;

If the literal is the maximum possible literal, a special case is triggered to properly trim the resulting subtraction.

Input:

  input x : SInt<2>
  output z : SInt<3>
  z <= add(x, SInt(-2))

now generates (after this PR)

  assign z = $signed(x) - 3'sh2;

* Updated documentation

* Change ArrayBuffer to ListBuffer

* Change name to minNegValue

* Remove mutable public interfaces

Co-authored-by: Albert Magyar <albert.magyar@gmail.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

Co-authored-by: Jim Lawson <ucbjrl@berkeley.edu>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

Co-authored-by: Jim Lawson <ucbjrl@berkeley.edu>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

* Add reviewer checklist / update contributor checklist

* Update PULL_REQUEST_TEMPLATE.md

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

Co-authored-by: Jim Lawson <ucbjrl@berkeley.edu>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

Co-authored-by: Jim Lawson <ucbjrl@berkeley.edu>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

Co-authored-by: Jim Lawson <ucbjrl@berkeley.edu>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

Co-authored-by: Jim Lawson <ucbjrl@berkeley.edu>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

Co-authored-by: Jim Lawson <ucbjrl@berkeley.edu>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>