Commits · 9b2f96b8d0b6c7f4e6fefde918d7a335ccd7b7f3 · github.com / freechipsproject / chisel3

Jul 31, 2015
- Updated lots of tests so they pass. Found one bug in expand whens · 9b2f96b8
  azidar authored Jul 30, 2015
  
  9b2f96b8
Jul 30, 2015
- Merge branch 'master' of github.com:ucb-bar/firrtl · d075e52e
  azidar authored Jul 29, 2015
  
  d075e52e
- Updated frontend changes · c442fe67
  azidar authored Jul 29, 2015
  
  c442fe67
- Added installation for linux · 55b8534d
  Adam Izraelevitz authored Jul 29, 2015
  
  55b8534d
- Added linux zip · c8196b01
  Adam Izraelevitz authored Jul 29, 2015
  
  c8196b01
- Finished supporting Chisel 2.0 Ref Chip · 7646c2e3
  Adam Izraelevitz authored Jul 29, 2015
  
  7646c2e3
- Add bigint support. · 6ce20db7
  Adam Izraelevitz authored Jul 29, 2015
  
  6ce20db7
Jul 29, 2015
- Integrated bigint. Mostly works, but getting "cast" error for make Test. · 0c7aca56
  Adam Izraelevitz authored Jul 28, 2015
  
  0c7aca56
Jul 23, 2015
- Fixed verilog so it emits non-random inital values. Changed Not to be · 69e4bc2c
  Adam Izraelevitz authored Jul 22, 2015
```
correct.
```
  69e4bc2c
Jul 22, 2015
- Firrtl generates verilog that compiles, but does not work · 5fadf121
  Adam Izraelevitz authored Jul 21, 2015
  
  5fadf121
- Fixed bug in fix :P · 86dfd891
  azidar authored Jul 21, 2015
  
  86dfd891
- Fixed removing non-referenced components · 306206f0
  azidar authored Jul 21, 2015
  
  306206f0
- Merge branch 'new-low-firrtl' of github.com:ucb-bar/firrtl into new-low-firrtl · d1c11b61
  azidar authored Jul 21, 2015
  
  d1c11b61
- Updated TODO · c093b68d
  azidar authored Jul 21, 2015
  
  c093b68d
- Made things go faster. Still in progress. Expand when now removes · c69a4573
  Adam Izraelevitz authored Jul 21, 2015
```
non-referenced declarations that are not instances, but it doesn't work
right now.
```
  c69a4573
Jul 18, 2015

Datapath compiles with Chisel 2.0 -> FIRRTL -> Verilog! · 70567d4d

Adam Izraelevitz authored Jul 17, 2015

Had to separate initialization check pass
Need to write dead code elimination pass
Added LongWidth to support dshl that are huge

70567d4d

Jul 17, 2015
- Merge branch 'new-low-firrtl' of github.com:ucb-bar/firrtl into new-low-firrtl · 98bb81d9
  azidar authored Jul 16, 2015
```
Conflicts:
	src/main/stanza/firrtl-ir.stanza
	src/main/stanza/passes.stanza
	src/main/stanza/verilog.stanza
```
  98bb81d9
- Fixed rename to work with chisel3 stuff · b7504759
  azidar authored Jul 16, 2015
  
  b7504759
Jul 15, 2015
- Fixed performance bug in backend. Added renaming · dad79768
  azidar authored Jul 14, 2015
  
  dad79768
- Added tests for clocks. Added remove scope and special chars passes. Added... · 271e1bf5
  azidar authored Jul 13, 2015
```
Added tests for clocks. Added remove scope and special chars passes. Added tests. Made more tests pass
```
  271e1bf5
- Added clock support · 0bfb3618
  azidar authored Jul 10, 2015
  
  0bfb3618
- Updated flo backend · 0d63d521
  azidar authored Jul 07, 2015
  
  0d63d521
- Passes riscv-mini tests · 1c3b45cc
  azidar authored Jul 07, 2015
  
  1c3b45cc
- Pass most tests. The ones that do not pass are not expected to, yet · d696dd01
  azidar authored Jul 07, 2015
  
  d696dd01
- Added chisel feedback to firrtl spec. Datapath_new triggers too large a width error · 3c8f283b
  azidar authored Jul 06, 2015
  
  3c8f283b
- Still partial commit, many tests pass. Many tests fail. · 68f7ac42
  azidar authored Jul 06, 2015
  
  68f7ac42
- Partial commit · 8d6c8307
  azidar authored Jul 02, 2015
  
  8d6c8307
- In progress commit · 52f2b8a0
  azidar authored Jul 02, 2015
  
  52f2b8a0
- Fixed bug in lowering, where the indexes to many-connects and accessors weren't lowered · f20d88a4
  azidar authored Jul 14, 2015
  
  f20d88a4
Jul 14, 2015
- Added tests for clocks. Added remove scope and special chars passes. Added... · 9b6d8514
  azidar authored Jul 13, 2015
```
Added tests for clocks. Added remove scope and special chars passes. Added tests. Made more tests pass
```
  9b6d8514
Jul 11, 2015
- Added clock support · 1ed6d4a4
  azidar authored Jul 10, 2015
  
  1ed6d4a4
Jul 08, 2015
- Updated flo backend · a62fea15
  azidar authored Jul 07, 2015
  
  a62fea15
- Passes riscv-mini tests · 521bac82
  azidar authored Jul 07, 2015
  
  521bac82
- Pass most tests. The ones that do not pass are not expected to, yet · df4bae5c
  azidar authored Jul 07, 2015
  
  df4bae5c
Jul 07, 2015
- Added chisel feedback to firrtl spec. Datapath_new triggers too large a width error · c8d1fc06
  azidar authored Jul 06, 2015
  
  c8d1fc06
- Still partial commit, many tests pass. Many tests fail. · d9ece539
  azidar authored Jul 06, 2015
  
  d9ece539
- Partial commit · 3145eaab
  azidar authored Jul 02, 2015
  
  3145eaab
- In progress commit · 903e5ba4
  azidar authored Jul 02, 2015
  
  903e5ba4
- Updated todo · 896f6a94
  azidar authored Jul 06, 2015
  
  896f6a94
Jul 03, 2015
- Added firrtl-lexer · a5727e67
  azidar authored Jul 02, 2015
  
  a5727e67