Still fails one test - DirectionSpec in Direction.scala

Need to convert UInt(x) into UInt.Lit(x) or UInt.width(x)

Compiles but fails tests.

Move more publishing definitions into commonSettings.

This should have been part of PR #194.

Add a hack to build.sbt to allow local publishing
We're merging this despite the failing tests (Jenkins ghprb isn't communicating with GitHub following security and authentication updates). We'd prefer to package all the sbt subprojects in a single jar, but current attempts to do so fail. See #208.

Until we sort out how to include the subproject classes in a single jar file, we need to explicitly publish all subprojects.

* chiselTests: include an example of two empty Vectors killing FIRRTL

* Aggregate: fix a bug whereby Vec[T] was using equals/hashCode of Seq

In Chisel, two vectors are NOT equal just if their contents are equal.
For example, two empty vectors should not be considered equal. This
patch makes Vec use the HasId._id for equality like other Chisel types.

Without this fix, Bundle.namedElts.seen: HashSet[Data]() will eliminate
one of the named vectors and emit bad IR.

Source locators

This prevents Verilator from erroring when it cannot determine the top-module.
It also changes the PRINTF_COND guard to correctly use the top-level reset
instead of just the top of the Chisel-generated code.

remove Tester.scala

RegNext and RegInit should match Reg(next=) and Reg(init=)

Option(null) returns None, but Some(null) returns Some(null)

Move emit out of IR

The return value of Bits.toBools doesn't need to be dynamically indexed
(as you could have just dynamically indexed the Bits itself), so
returning a Seq instead of a Vec is mroe appropriate.

This breaks a circular dependence between Bits and Vec, which helps
with macros/frontend refactoring.

Include Chisel Frontend in JAR