- Aug 02, 2017
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Donggyu authored
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- Jul 27, 2017
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Andrey Ayupov authored
* initial implementation of InlineDeepTransformation * rewrote transformation to not have any side effects in terms on inlining that was not annotated to be inlined * minor rewrites * renamed transformations to Flatten * fixes according to review * added more comments and fixed formating/style * fixed spacing, minor style fixes
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- Jul 19, 2017
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Jack Koenig authored
Fix ConstProp bug where multiple names would swap with one
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- Jul 18, 2017
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Donggyu Kim authored
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Jack Koenig authored
Fixes issue in https://github.com/freechipsproject/rocket-chip/pull/848
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- Jul 15, 2017
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Jack Koenig authored
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- Jul 07, 2017
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Chick Markley authored
* Fixed inability to disable combo loop check Moved checking of dontCheckComboLoops into loadAnnotations so that it works in cases where Driver.execute is not used. * Fix test for annotations, modifications to loadAnnotations made 2 more annotations visible. * Remove debug println from DriverSpec
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- Jul 04, 2017
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Jack Koenig authored
Const prop regs
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- Jun 30, 2017
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Jack Koenig authored
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Jack Koenig authored
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Jack Koenig authored
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Jack Koenig authored
Preserve "better" names in Constant Propagation
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Jack Koenig authored
Names that do not start with '_' are "better" than those that do
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Jack Koenig authored
Use Travis Build Stages
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Jack authored
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Jack authored
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Jack Koenig authored
Improvements to Constant Propagation and Testing
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- Jun 29, 2017
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Jack Koenig authored
Constant Propagation will not optimize across components marked dontTouch
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Jack Koenig authored
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Jack Koenig authored
This makes it more concise to write tests
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Jack Koenig authored
Gives all transform specs access to useful utilities (like dontTouch). Deletes some duplicate code. Parsing mode UseInfo is fine for everything, only matters if the test actually uses info.
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Jack Koenig authored
Remove reset and fix bug in register update Verilog emission
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- Jun 28, 2017
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Jack Koenig authored
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Jack Koenig authored
Fixes bug where the Verilog emitter could pull the next value for a register that feeds a second register, removing the first register from the second register's update.
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- Jun 27, 2017
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Jack Koenig authored
This requires a quick second pass to back propagate constant wires but the QoR win is substantial. We also only need to count back propagations in determining whether to run ConstProp again which shaves off an iteration in the common case.
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Jack Koenig authored
Similar to #543
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- Jun 22, 2017
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Jack Koenig authored
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- Jun 14, 2017
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Jack Koenig authored
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Jack Koenig authored
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Jack Koenig authored
Also add tests for what should happen to 'is invalid' in ExpandWhens Fixes #606
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Jack Koenig authored
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- Jun 13, 2017
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Jack Koenig authored
Resolves #600
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Jack Koenig authored
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Jack Koenig authored
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Shreesha Srinath authored
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- Jun 09, 2017
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Colin Schmidt authored
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- Jun 07, 2017
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Colin Schmidt authored
* Display the total time firrtl took to compile * Switch timing print out to error(aka default)
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- May 31, 2017
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Jack Koenig authored
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Jack Koenig authored
Makes Verilog more readable to both humans and scripts
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- May 28, 2017
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Jim Lawson authored
* Update dependencies and JavaConverters for Scala 2.12 * Bump Scala (and library) version(s). * replace "error" with "Utils.error"; bump Scala version to 2.11.11
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