* Fixes #1505

* See freechipsproject/chisel3#1408

Add a Treadle build to the portion of CI that runs Chisel3 tests.
Chisel3 needs to have a master copy of Treadle in order for it to
work and cannot rely on resolution from Maven.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

Move new transforms, recently added, into existing or new sets of
transforms (defined in firrtl.stage.Forms).

One transform is a mandatory low FIRRTL optimization:

  - firrtl.transforms.LegalizeAndReductionsTransform

Previously, this was included as a prerequisite of all Verilog
emitters (minimum, normal, and SystemVerilog).

Two transforms associated with converting and removing the new
verification statements are moved into a new set of transforms,
AssertsRemoved:

  - firrtl.transforms.formal.ConvertAsserts
  - firrtl.transforms.formal.RemoveVerificationStatements

Previously, these transforms were directly added as prerequisites to
the minimum Verilog and normal Verilog emitter, but not the
SystemVerilog emitter.

The designation of inputForm=LowForm for legacy, custom transforms is
updated to include assertion removal transforms as part of their
optionalPrerequisites. This has the effect of continuing to cause
inputForm=LowForm transforms to run as late as possible (right before
the low FIRRTL, minimum Verilog, Verilog, or SystemVeriog emitter).

Tests are updated to reflect the new order in both CustomTransformSpec
and LoweringCompilersSpec.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

* add sign-extend const-prop test

* Emitter: don't wrap Neg operand in concat

* add const prop bitwise reduction equivalence test

* mask negative literals when propagating reduction

* change widths

* get rid of unnecessary if

* add BigInt mask utility

* ConstProp: test bitwise op of signed literals

* ConstProp: use bit mask for FoldOr/FoldXor

* handle and also

* add UIntLiteral.masked helper

Co-authored-by: Jack Koenig <koenig@sifive.com>

* test const prop of addition of negative literals

* Emitter: handle minimum negative values correctly

* update expected verilog in AsyncResetSpec

Change the class-global, but private ConstraintSolver object inside
InferWidths to instead be constructed on each execute invocation. This
prevents issues with thread safety where running the same InferWidths
object at the same time would cause the ConstraintSolver to get
trampled on.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

* dedup: add faster InstanceGraph implementation and use it in dedup

The new implementation takes care not to hash the instance
types contained in DefInstance nodes.
This should make dedup considerably faster.

* FastInstanceGraph: cache vertices for faster findInstancesInHierarchy

* FastInstanceGraph: remove the parent name field since it isn't actually necessary

* FastInstanceGraph -> InstanceKeyGraph

* InstanceGraph: describe performance problems.

* InstanceKeyGraph: turn moduleMap into a def instead of a val

This will make changing implementation details much easier
in the future.

* InstanceKeyGraph: return childInstances as Seq instead of Map

This ensures a deterministic iteration order and it
can easily be turned into a Map for O(1) accesses.

* InstanceKeyGraph: add tests for public methods

* InstanceKeyGraph: group public methods together

* InstanceKeyGraphSpec: fix wording of a comment

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

Add cross-building of unidoc to test issues if a user later does a
+publishLocal (like with Chisel CI).

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

Fix Fuzzer for 2.11

This fixes two issues with the Fuzzer when running '+publishLocal':

- Avoid foo(_) pattern due to weaker 2.11 type inference
- Use seqAsJavaListConverter instead of seqAsJavaList (a 2.12
  addition)

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

* [WIP] Propagate source locators to Verilog if-else emission

* Add and fix tests for reg update info propagation

* Add limited source locator propagation in ConstProp

Support propagating source locators on connections or nodes where the
right-hand side is simply a reference. This case comes up a lot for
registers without a synchronous reset.

node _T_1 = x @[MyFile.scala 12:10]
node _T_2 = _T_1
z <= x

Previousy the source locator would be lost, now the result is:

z <= x @[MyFile.scala 12:10]

* Address review comments

Co-authored-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

Co-authored-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

Includes:
* Random generator of FIRRTL Expressions (UInt and SInt types)
* JQF SBT plugin and CLI
* Documentation in README.md

Co-authored-by: Jack Koenig <koenig@sifive.com>

Remove overlapping inputForm=LowForm tests

Refactor the test used in the CustomTransformSpec to assert that
inputForm=LowForm legacy transforms run right before the emitter (see
note below!). The new test looks only for a list of (customTransform,
emitter) in a sliding, size-2 window of the flattened transform order.
Previously, this was looking for a match before and after the custom
transform. The old implementation necessitate busywork updates of the
test when new transforms are added that changed the transform running
before the custom transform.

Note: this test, as written is intentionally wrong. When verification
statements were added, the test was changed to not do what it's
supposed to do. Namely, the test is supposed to ensure that an
inputForm=LowForm transform runs immediately before its emitter.
However, the test is actually checking that the custom transform runs
before transforms that convert and remove verification statements. I'm
intentionally leaving the test broken, but doing the refactor in order
to...

Remove tests from LoweringCompilerSpec testing the placement of
inputForm=LowForm legacy, custom transforms. This behavior is already
tested in the CustomTransformSpec.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

This should speed up the common case
as the compiler never operates on the
unescaped string.
The new escape function also fixes a bug
where ']' was not escaped even though it
is the delimiting character for FileInfo.
In order to maintain backwards
compatibility for the ProtoBuf format,
this patch adds escape/unescape calls
when going from/to protobuf format.
For better performance we should consider
changing the protobuf format.

Add an optionalPrerequisiteOf to TopWiringTransform pointing at
LowerTypes.

This fixes a bug where top-wired wire bundles with flips could result
in the top-wired, flattened bundle having every field with an "output"
direction if the TopWiringTransform is moved around in the transform
order (see FIRRTL issue #1744).

Why did this happen?

Fundamentally, this stems from the fact that LowerTypes preserves
bundle direction for ports, but destroys it for wires.

Specifically, The TopWiringTransform creates ports of the "output"
direction that are copies of the underlying type of the component
being top-wired. Before LowerTypes, the type of a bundle has direction
information via flips. After LowerTypes, the lowered ground type does
not have this information. Therefore, all the ports are ground type
outputs. Simply ensuring that TopWiringTransform must run before
LowerTypes avoids this problem.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

* Drop plugin
* Drop make recipe

For multi-line registers, the parsed source locator is located in a
different place in the concrete syntax tree than it is for other
Statements.

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

* Define 'same clock' in a syntactic sense

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

Changed from target/<scala-version>/src_managed/main/firrtl/ to
target/<scala-version>/src_managed/main/compiled_protobuf/firrtl/
The protobuf generation clears its target directory so it would clear
the generated ANTLR-generated files.

* add .bloop and .metals to .gitignore

* add project/metals.sbt to .gitignore

* RemoveAccess: update gender to flow

* ExpandWhens: update female to sink

* RemoveCHIRRTL: female -> sink, male -> source

* benchmark: add hot.DedupBenchmark

* dedup: use structural md5 hash instead of agnostify and serialize

* StructuralHash: generate PrimOp LUT

* StructuralHash: change MessageDigestHasher to not be a case class

* StructuralHash: we want Blocks and EmptyStmt to be ignored

* StructuralHash: use SHA-256 instead of MD5

* StructuralHash: clarify extmodule port name agnistification

* StructuralHash: hash the name of width vars instead of trying to agnostify

This should be in line with the old Dedup behavior.
The prior use of n(..) was incorrect since the namespace
of these vars is different from the normal module scope namespace.

* StructuralHash: address Schuyler's review comments

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

This Serializer which is implemented
external to the IR node definition
uses a StringBuilder to achieve about a
1.7x performance improvement when serializing.

Eventually, all implementations of the
`serialize` methd should be replaced with
a call to `Serializer.serialize`.

However, for this PR we keep the old
code in place in order to allow for easy
regression testing with the benchmark JAR
like this:
> java -cp utils/bin/firrtl-benchmark.jar \
  firrtl.benchmark.hot.SerializationBenchmark \
  ~/benchmarks/medium.pb 2 5 test

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

Fix a bug where a type check would always yield true. This caused a
bug where allow/block-list annotations would be incorrectly applied to
all subtypes of ManipulateNames.

The tests are updated to check that this now works.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

* Add testcase for empty message

* ConvertAsserts maps each assert into a gated print-and-stop
* ConvertAsserts is an optional prereq of RemoveVerificationStatements
* ConvertAsserts generates Low FIRRTL
* Drop print for asserts that have an empty message
* Fix scaladoc formatting from review

Co-authored-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

* Batch renames in LowerTypes

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

* Add benchmarking for LowerTypes

Add infrastructure of benchmarking Transforms (in addition to
existing infra for Passes). Also run System.gc between each timed
benchmark to improve stability.

Co-authored-by: Jack Koenig <koenig@sifive.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

Refactor ManipulateNames to use Target

Adds an options to the FIRRTL compiler command line to schedule the
LowerCaseNames and UpperCaseNames transforms.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

This adds three new transforms:

  - (abstract) LetterCaseTransform parent of case manipulation
  - LowerCaseNames to lower case all names
  - UpperCaseNames to upper case all names

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>