1. Feb 06, 2019
  2. Feb 05, 2019
  3. Feb 02, 2019
  4. Feb 01, 2019
  5. Jan 29, 2019
    • Sequencer's avatar
      typo fix (#1001) · f15736eb
      Sequencer authored
      make more clear for ExecutionOptionsManager log level settings.
      f15736eb
  6. Jan 27, 2019
  7. Jan 24, 2019
    • Andrew Waterman's avatar
      Improve Shl codegen; eliminate Shlw WIR node (#994) · 1738c1ef
      Andrew Waterman authored
      * Improve Shl codegen; eliminate Shlw WIR node
      
      If we emit shl(x, k) as {x, k'h0} instead of (x << k), then there's
      no need for Verilog-specific padding in the PadWidths pass.  Avoiding
      the redundant padding improves compiler/simulator performance and
      renders Shlw unnecessary.
      
      * [skip formal checks] Add test
      1738c1ef
  8. Jan 23, 2019
  9. Jan 22, 2019
  10. Jan 16, 2019
  11. Jan 15, 2019
  12. Jan 14, 2019
  13. Jan 08, 2019
    • Jim Lawson's avatar
      Avoid enforcing time constrains during coverage tests. (#989) · 5f0e893c
      Jim Lawson authored
      This fixes issue #988
      I tried one alternative to this fix: record the time to do a *no rename* run (`depth = 0`) and check that the time to do the *deep rename* (`depth = 500`) was a reasonable multiple of the *no rename* test. Unfortunately, the discrepancies were all over the map, sometime as much three orders of magnitude difference.
      I decided the current fix was the simplest - don't enforce timing checks if we're doing coverage testing, although determining the latter is brittle.
      5f0e893c
  14. Jan 05, 2019
  15. Jan 03, 2019
    • Jack Koenig's avatar
      Make GroupComponents run ResolveKinds · 8bc25bbc
      Jack Koenig authored
      This fixes an issue where expressions created by GroupComponents would
      be improperly lowered because they were not marked as references to
      instance ports.
      8bc25bbc
  16. Dec 26, 2018
  17. Dec 22, 2018
  18. Dec 21, 2018
  19. Dec 20, 2018
    • Schuyler Eldridge's avatar
      Add IdentityTransform · f11a0f03
      Schuyler Eldridge authored
      
      
      This adds an identity transform that applies an identity function to some
      CircuitState, i.e., it just returns the original CircuitState. This is
      useful for transform generators that may, for edge cases, generate an
      empty transform sequence. Other classes (e.g., Compiler) have explicit or
      implicit requirements that a transform sequence is non-empty.
      
      Signed-off-by: default avatarSchuyler Eldridge <schuyler.eldridge@ibm.com>
      f11a0f03
  20. Dec 19, 2018
  21. Dec 14, 2018
  22. Dec 12, 2018
  23. Dec 07, 2018