[skip formal checks]
Generate nicer name for remove accesses

Fixes #527 

This resulted in parent modules sometimes being constant proppagated
before a child module. If the child module has a constant driving one of
its outputs, the parent module would thus not see the constant. This
resulted in strange unstable constant propagation behavior where
sometimes constant outputs would not propagate.

Also add test illustrating why this occurs with uses of InstanceGraph

Fixes #708

Bump SBT to 1.0.4 and update plugins
Update Scala versions and sbt commands in .travis.yml
Replace run-main with runMain

Remove wires, replacing them with nodes

Make the check script allow different designs
Add FPU, ICache, and RocketCore to regress and use instead of Rob for CI
equivalence check

This transform replaces all wires with nodes in a legal, flow-forward
order

Move pad to object ConstantPropagation so other transforms can use it

* add graph node classes

* add graph representation usage pass

* remove pass using graph nodes so that firrtl can compile

* move google graph ir nodes to altIR package

Also let Travis know that equivalence checks can take a while

Add Yosys formal equivalence checking to Travis regressions

Also add Travis test for running this script on PRs

Defined as the range from ' ' to '~' [0x20, 0x7e]

This prevents collisions for one prefix (including temp) from
incrementing the suffix for other prefixes. Makes names more stable.

Refactor StringLit to use String instead of Array[Byte]

When calling verilator in a subdirectory like ./test_run_dir/...
verilator will read the verilog file from the current working directory
if there is a file there with the right name.  This fix specifies
the specific path of the verilog file intended.

not exit when --help is included in program flags

Adds programArgs to commonOptions
programArgs is all arguments on command line with out leading -/+
or are not bound to a flag.
Create simple test