Defined as the range from ' ' to '~' [0x20, 0x7e]

This prevents collisions for one prefix (including temp) from
incrementing the suffix for other prefixes. Makes names more stable.

Refactor StringLit to use String instead of Array[Byte]

When calling verilator in a subdirectory like ./test_run_dir/...
verilator will read the verilog file from the current working directory
if there is a file there with the right name.  This fix specifies
the specific path of the verilog file intended.

not exit when --help is included in program flags

Adds programArgs to commonOptions
programArgs is all arguments on command line with out leading -/+
or are not bound to a flag.
Create simple test

* Update sbt to 0.13.16; add Scala 2.12 support.
To clean, test, and build Scala 2.11 and Scala 2.12 versions:
  % sbt +clean +test +publishLocal

* Update Travis to test in 2.11.11 and 2.12.3

* Try different way of providing Travis Scala version

* Attempt to get verilator built before tests.

* Make pathsInDAG walk all possible paths

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

* Use linearization order when finding all paths in DAG

Since InstanceGraph now has all modules in its graph, test ConstProp on all modules as a default behaviour.

- Need to think about how to target ConstProp only for a specific module?

Close #644

* Added option to emit final annotations

* Removed extra > from output-anno-file

* Removed other extra > from input-anno-file

* Reorder port and wire assignments in Verilog

* Fixed up syntax

bug fix for cases when we want to flatten a module in which a module is instantiated multiple times (#634)

* initial implementation of InlineDeepTransformation

* rewrote transformation to not have any side effects in terms on inlining that was not annotated to be inlined

* minor rewrites

* renamed transformations to Flatten

* fixes according to review

* added more comments and fixed formating/style

* fixed spacing, minor style fixes

Fix ConstProp bug where multiple names would swap with one

Fixes issue in https://github.com/freechipsproject/rocket-chip/pull/848

* Fixed inability to disable combo loop check
Moved checking of dontCheckComboLoops into loadAnnotations so
that it works in cases where Driver.execute is not used.

* Fix test for annotations, modifications to loadAnnotations
made 2 more annotations visible.

* Remove debug println from DriverSpec

Const prop regs

Preserve "better" names in Constant Propagation

Names that do not start with '_' are "better" than those that do

Use Travis Build Stages

Improvements to Constant Propagation and Testing

Constant Propagation will not optimize across components marked
dontTouch

This makes it more concise to write tests

Gives all transform specs access to useful utilities (like dontTouch).
Deletes some duplicate code. Parsing mode UseInfo is fine for
everything, only matters if the test actually uses info.

Remove reset and fix bug in register update Verilog emission