Add ranging API

Also restrict black boxes to not allow hardware inside of them since it was
being silently dropped anyway.

Resolves #289

Workaround for:
http://www.veripool.org/issues/1101-Verilator-Fix-SmallName-for-ParamTypeDType

Also, remove no-longer-special case for n=1.

Eliminate some doc warnings

Implemented by adding a Boolean to check for alternating invocations of object
Module.apply and the constructor of abstract class Module.
Fixes #192

Prefix temporary names with underscores so Verilator won't trace them
Use verilator argument "--trace-underscore" if you want to trace these
signals

defaultCompileOptions is convenient, but it frequently foils the
compatibility layer by providing strict defaults rather than passing
through the user's CompileOptions.  This notably manifests for
chiselCloneType, which has different behavior for chisel3 and Chisel.

Ideally, we'd get rid of defaultCompileOptions within chisel3.core
and only supply it to people who import chisel3._ (attn. @ucbjrl).
That would statically prevent further regressions of this nature
within the core.

The change to Vec.truncateIndex seems extraneous, but I chose an
alternate implementation rather than requiring compileOptions in
another place.

f1507aa7 triggers a rocket-chip
regression, because Chisel used to not preserve flippedness on
cloneType.

fix SeqMem's read port creation