- Sep 02, 2016
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Jim Lawson authored
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- Aug 31, 2016
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Jim Lawson authored
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Jim Lawson authored
Remove references to the Chisel package in favor of explicit chisel3 imports in tests,
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Jim Lawson authored
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Jim Lawson authored
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Jim Lawson authored
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Jim Lawson authored
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- Aug 30, 2016
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Jim Lawson authored
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Jim Lawson authored
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Jim Lawson authored
Import chisel3.NotStrict.CompileOptions in Chisel package. Add CompileOptions tests.
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Jim Lawson authored
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Jim Lawson authored
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Jim Lawson authored
Stricter values are "true". Current default (not strict) values are "false".
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- Aug 26, 2016
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Chick Markley authored
Public APIs for chisel object names
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Donggyu Kim authored
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Jim Lawson authored
Use bulkConnect in Vec,fill if any (flattened) element of the Vec has a direction associated with it. This impetus for this came out of discussion during the chisel meeting of 8/24/16 in response to errors running the chisel tutorial examples Adder test.
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- Aug 25, 2016
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chick authored
signalName -> instanceName SignalId -> InstanceId Based on Stephen's comments on PR
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- Aug 24, 2016
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Jim Lawson authored
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- Aug 23, 2016
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Jim Lawson authored
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Jim Lawson authored
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- Aug 22, 2016
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chick authored
Removed extraneous logic Renamed doStuff to buildAnnotatedCircuit Removed println's
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chick authored
Add AnnotationSpec file which provides an example of a way to implement generation of annotations in a chisel circuit that could be used by custom firrtl passes This spec also shows and tests in a limited way the new API of .signalName, .pathName, parentModName which allows access to the various path information of a chisel component (something that subclasses SignalId, most prominently SubClasses of Data and Module
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chick authored
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Donggyu Kim authored
* signalName: returns the chirrtl name of the signal * pathName: returns the full path name of the signal from the top module * parentPathName: returns the full path of the signal's parent module instance from the top module * parentModName: returns the signal's parent **module(not instance)** name.
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- Aug 20, 2016
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Jim Lawson authored
Input, Output, and Flipped clone their inputs.
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Jim Lawson authored
As a side-effect, handle BlackBoxes correctly.
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- Aug 19, 2016
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Jim Lawson authored
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Jim Lawson authored
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Jim Lawson authored
Revive support for firrtl flip direction. Remove compileOptions.internalConnectionToInputOk
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- Aug 18, 2016
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Jim Lawson authored
Assume LHSItOutput if neither side is driving. Restore Wire()'s removal of direction in binding.
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Jim Lawson authored
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- Aug 17, 2016
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Jim Lawson authored
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Jim Lawson authored
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Jim Lawson authored
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- Aug 16, 2016
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Andrew Waterman authored
* Make "def width" a private API; expose isWidthKnown instead Resolves #256. Since width was used to determine whether getWidth would succeed, I added def isWidthKnown: Boolean but another option would be to expose something like def widthOption: Option[Int] ...thoughts? * Document getWidth/isWidthKnown * Add widthOption for more idiomatic Scala manipulation of widths
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- Aug 13, 2016
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Jim Lawson authored
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Jim Lawson authored
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Jim Lawson authored
Nothing uses these now, but when we integrate Stephen's PR200, we'll need a way to selectively enable some strict connection checks on a file by file basis. We plan to do this using package imports which will define suitable compilation options.
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- Aug 12, 2016
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Jim Lawson authored
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- Aug 10, 2016
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Andrew Waterman authored
The API allowed this before, but not safely, as users could create name conflicts. This exposes the pre-deduplication/sanitization naming API, and closes the other one.
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