- Apr 05, 2022
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Jack Koenig authored
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- Apr 02, 2022
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fzi-hielscher authored
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- Mar 31, 2022
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Jack Koenig authored
This reduces memory use of every HasId by 64 bytes. Every instance of HasId (including all Data) had 2 ListBuffer vals for recording post-naming hooks, yet this feature is almost never used. These are now vars of type List which allows the common case of Nil to add no incremental memory use per instance of HasId.
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- Mar 26, 2022
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Schuyler Eldridge authored
Signed-off-by:Schuyler Eldridge <schuyler.eldridge@sifive.com>
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- Mar 23, 2022
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Megan Wachs authored
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- Mar 16, 2022
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Jack Koenig authored
This reverts commit 3c8a810e.
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Scala Steward authored
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- Mar 15, 2022
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Jack Koenig authored
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Adam Izraelevitz authored
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Scala Steward authored
Co-authored-by:mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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Scala Steward authored
Co-authored-by:mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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Scala Steward authored
Co-authored-by:mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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- Mar 10, 2022
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Jack Koenig authored
Also delete an errant println in InstanceSpec
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Jared Barocsi authored
Chisel <> semantics differ somewhat from FIRRTL <= semantics, so we only emit <= when it would be legal. Otherwise we continue the old behavior of emitting a connection for every leaf-level Element. Co-authored-by:
Deborah Soung <debs@sifive.com> Co-authored-by:
Jack Koenig <koenig@sifive.com>
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- Mar 08, 2022
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Liu Xiaoyi authored
Co-authored-by:
Jiuyang Liu <liu@jiuyang.me> Co-authored-by:
Megan Wachs <megan@sifive.com> Co-authored-by:
Jack Koenig <koenig@sifive.com>
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- Mar 07, 2022
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Megan Wachs authored
* Tweaks to the Verilog-vs-Chisel Page * Update cookbook.md * Update verilog-vs-chisel.md * Update verilog-vs-chisel.md
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- Mar 05, 2022
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Megan Wachs authored
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- Mar 04, 2022
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Andrew Waterman authored
* Issue errors on out-of-range extracts when width is known Firrtl will catch this later on, but better to error early if possible. * Test that errors are generated on OOB extracts when width is known
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Olushola Ogunkelu authored
Co-authored-by: Shola Ogunkelu @Shorla Co-authored-by:
Megan Wachs <megan@sifive.com> Co-authored-by:
Deborah Soung <debs@sifive.com> Completed as part of Outreachy Internship Dec 2021-March 2022.
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- Feb 16, 2022
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Jiuyang Liu authored
Widths are now padded to the maximum width of the inputs. Co-authored-by:Jack Koenig <koenig@sifive.com>
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- Feb 13, 2022
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Aditya Naik authored
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- Feb 12, 2022
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Deborah Soung authored
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- Feb 10, 2022
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Megan Wachs authored
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Megan Wachs authored
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- Feb 09, 2022
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Carlos Eduardo authored
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- Feb 04, 2022
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Tynan McAuley authored
Co-authored-by:mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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Jack Koenig authored
* Only call _elementsImpl once in Bundle.elements * Distinguish compiler plugin and reflective _elementsImpl Bundle.elements now will only do post-processing if the user is using plugin-generated _elementsImpl. This improves performance for the case where the user does not opt-in to using the plugin to generate _elementsImpl.
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John Ingalls authored
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- Feb 03, 2022
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Jack Koenig authored
* Change type of Bundle._elementsImpl to Iterable It was previously SeqMap (ListMap on Scala 2.12). This change gives us more freedom to optimize the implementation without breaking binary compatibility. It is scala.collection.Iterable because it is perfectly fine to return mutable collections (like Arrays) since the only use is to Iterate on them. * Disallow users implementing Bundle._elementsImpl Currently, it would result in a runtime linkage error. This turns it into a compile-time error. Co-authored-by:mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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Jack Koenig authored
Use Builder.deprecated instead of Builder.warning so that the warnings are aggregated by source locator to prevent spamming the screen with duplicated warnings.
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- Feb 02, 2022
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Jack Koenig authored
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Aditya Naik authored
Warn if clock at memory instantiation differs from clock bound at port creation and port clock is not manually passed Co-authored-by:Jack Koenig <koenig@sifive.com>
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Chick Markley authored
Adds generation of `Bundle.elements` method to the chores done by the compiler plugin For each `Bundle` find the relevant visible Chisel field members and construct a hard-coded list of the elements and their names implemented as `_elementsImpl` For more details: See plugins/README.md - Should be no change in API - Handles inheritance and mixins - Handles Seq[Data] - Tests in BundleElementSpec Co-authored-by:
chick <chick.markley@sifive.com> Co-authored-by:
Jack Koenig <koenig@sifive.com>
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Jack Koenig authored
* Do not trim stack traces of exceptions with no stack trace This prevents us from accidentally giving stack traces to exceptions that don't have them and giving misleading messages telling users to use --full-stacktrace when it won't actually do anything. Also deprecate ChiselException.chiselStackTrace which is no longer being used anywhere in this codebase. * Add exception class for multiple-errors reported New chisel3.internal.Errors replaces old anonymous class that would show up as chisel3.internal.ErrorLog$$anon$1 in error messages. * Add new option --throw-on-first-error This tells Chisel not to aggregate recoverable errors but instead to throw an exception on the first one. This gives a stack trace for users who need it for debugging.
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- Jan 30, 2022
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Scala Steward authored
Co-authored-by:mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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- Jan 29, 2022
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Jiuyang Liu authored
This reverts commit 4097d179 . Co-authored-by:
mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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Jiuyang Liu authored
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- Jan 28, 2022
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Scala Steward authored
Co-authored-by:mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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Scala Steward authored
Co-authored-by:mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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Scala Steward authored
Co-authored-by:mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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