Added tests for clocks. Added remove scope and special chars passes. Added tests. Made more tests pass

Fixed fir files so they correctly compile to verilog! Front-end needs to generate as-SInt instead of convert, always. Added fast build to Makefile

Changed Core.fir so dshl wasn't huge. Fixed padding pass to preserve correct low-firrtl syntax. Generates verilog that compiles, but is not correct

fix pad/trimming pass and fix bits-select width inference bug

Added sequential/combinational memories. Started debugging verilog backend. Added Long support so UInt(LARGENUMBER) works