- Apr 11, 2023
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Deborah Soung authored
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Deborah Soung authored
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Deborah Soung authored
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Deborah Soung authored
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Deborah Soung authored
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- Apr 07, 2023
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Deborah Soung authored
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Deborah Soung authored
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- Apr 06, 2023
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Deborah Soung authored
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Deborah Soung authored
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Deborah Soung authored
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Deborah Soung authored
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- Apr 05, 2023
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Schuyler Eldridge authored
Deprecate ChiselStage$.elaborate as this exposes internal Chisel APIs, namely "chisel3.internal.firrtl.Circuit". Replace usages of this in tests with emitCHIRRTL. Signed-off-by:Schuyler Eldridge <schuyler.eldridge@sifive.com>
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Jack Koenig authored
* Change many tests from simulation-based to checking the CHIRRTL. * Move tests that were hard to convert to new VecIntegrationSpec in integration-tests
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- Apr 04, 2023
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Jack Koenig authored
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Aditya Naik authored
Co-authored-by:Jack Koenig <koenig@sifive.com>
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Megan Wachs authored
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Megan Wachs authored
* mdoc-ify intrinsic explanation * Update docs/src/explanations/intrinsics.md * Update intrinsics.md
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- Apr 03, 2023
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Andrew Lenharth authored
* IntModule * intmodule works * a bit of documentation * formatting * example and better test. Rename all the things, now they are Blue! * formatting * typo * move file * indexes * Update core/src/main/scala/chisel3/internal/firrtl/IR.scala Co-authored-by:
Schuyler Eldridge <schuyler.eldridge@gmail.com> * Update docs/src/explanations/intrinsics.md Co-authored-by:
Schuyler Eldridge <schuyler.eldridge@gmail.com> * Update docs/src/explanations/intrinsics.md Co-authored-by:
Schuyler Eldridge <schuyler.eldridge@gmail.com> * simplify tests --------- Co-authored-by:
Schuyler Eldridge <schuyler.eldridge@gmail.com>
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- Apr 01, 2023
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George Lyon authored
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George Lyon authored
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- Mar 30, 2023
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Schuyler Eldridge authored
Change FIRRTL Circuit conversion/serialization to place ChiselAnnotations (converted to FIRRTL Annotations) inside the FIRRTL Circuit and to serialize this using the "%[[]]" inline JSON format that is present in the FIRRTL spec. This does not remove _all_ annotations passed via the annotation file, but it is the first step towards that.
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George Lyon authored
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- Mar 29, 2023
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George authored
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- Mar 28, 2023
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Adam Izraelevitz authored
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George Lyon authored
* Add low-level svsim based simulation to Chisel * Add Peek/Poke API
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- Mar 24, 2023
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Jack Koenig authored
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George Lyon authored
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George authored
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George authored
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- Mar 22, 2023
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Jack Koenig authored
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Jack Koenig authored
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George Lyon authored
Introduce `svsim`, a low level library for simulating SystemVerilog using Verilator and VCS. (#3121)
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Jack Koenig authored
Also run formatting on SBT files.
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George Lyon authored
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- Mar 21, 2023
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Sean Jensen-Grey authored
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Jack Koenig authored
Directly subclassing Iterable is lazy-ish, but if you call any operation on the resulting value (eg. map or ++) it will evaluate the Iterable and return a List.
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- Mar 19, 2023
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jensengrey authored
Co-authored-by:
Jack Koenig <koenig@sifive.com> Co-authored-by:
mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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Aditya Naik authored
Use new private Record._elements to validate Record elements. This allows us to check invariants earlier than on cloning or binding.
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Adam Izraelevitz authored
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Jack Koenig authored
It seems that deprecations on methods that are macro expanded away do not actually trigger a deprecation warning. Instead, we will just accept no source locator on the deprecated API (no released version of Chisel has the source locator).
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