Revert to more of original design (reduce exception interception), but intercept at a higher level.
Remove waiting.acquire() in run() method in exception processing so we get to call threadFinished() and scheduler() after the thread's demise.
Synchronize access to allThreads.
Move thread manipulation code into ThreadedBackend - killAllTesterThreads().

Eliminate hang on failure.
Clear errors before test start and report them at test end.

Add JNITestAPI.java interface and cpp implementation.
We need to use System.load() to load the compiled (but fixed) cpp code,
but use dlopen/dlsym/dlclose in the fixed cpp code to load the shared library since Java doesn't provide an explicit unload (dlclose) mechanism.
Tease apart the pieces im sim_api.h so we can use them from both separate process ans shared library verilator implementations.
Remove unused imports.
Modify the generated verilator <Module>.mk to add rules to build shared library version of the simulator.
Use multiline string literal to compose the harness code.
Much cleanup and testing required.
TODO:
 - we hang un failed expects with some possibly JNI related semaphore.
 - break up finish/abort/unload so they're composable.

Cache unadulterated signal names (don't add dut.name).
This will not work if we try to access signals for nested modules, but I don't think the current code supports that anyway. Add whatever prefix is required for the specific backend when we interrogate it for the actual signal.
Fix getDataNames() so it doesn't automatically add the top level name for an aggregate since these don't exist in some simulation environments (i.e., we need to synthesize them from their actual components).
Set the targetDirName something other than "."
Add scoping to resource names.
Support firrtl and verilator backends for BasicTest.scala.

Copy resources from chisel-testers.

Use TesterOptionsManager.
Use backendName to choose tester backend.
Rename VCS/Verilator tester backends.
Provide basic commend editing support.

* Update in light of annotations refactor.
Fix for freechipsproject/firrtl#721 and freechipsproject/chisel3#767.

* Respond to review comments - simplify annotations.

* Generalize ChiselAnnotation

This allows us to delay creation of Annotations till elaboration is
complete. Also update all annotation-related code.

* Add RunFirrtlTransform

Use a Chisel-specific RunFirrtlTransform API to preserve behavior of old
ChiselAnnotation (now called ChiselLegacyAnnotation)

* Use unique test directories in ChiselRunners.compile

Workaround for https://github.com/freechipsproject/firrtl/issues/731

Add companion objects to macro classes

Workaround for unconditional invalidation of macro classes in
incremental recompilation

* Remove checkboxes from issue/pr templates.

* Compact template text and try to make meta information comments.

* Respond to comments - remove bullet point usage.

Revert "Aggregate coverage - discover a working combination of aggregate usage to enable coverage of subprojects. (#782)" (#786)

This is still broken - it publishes multiple jars.
This reverts commit e08da912.