Problem: MemConf serialization of MemPorts was not deterministic
and the ordering seems to have changed as we move projects to 2.13
Downstream project can be adversely affected by changes in ordering
This changes specifies as specific ordering that should be compatible with
the historical one.

It is unclear if having more than one circuit annotation even works. If
it does, it is implausible that they would have the same circuit name
since that would correspond to a namespace collision.

Update `findTypeHints` to allow for the "class" field in JSON objects to
appear anywhere in the object. This used to rely on the field being the
very first in the object, which is easily violated when reading JSON
data generated externally, since an object's order of fields is
unspecified and can be arbitrarily scrambled.

Fixes #2497.

Before it would just download another copy of the PDF every time I wanted to go visit the spec repo.

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Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

This removes the FIRRTL specification as this now lives in its own
repository:

    https://github.com/chipsalliance/firrtl-spec



All git history (excluding binary updates to spec.pdf) have been
migrated to the new repository.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

This fixes handling of signed modulus and removes some redundant work.

- Convert FIRRTL spec to Markdown file.
- Add PDF generation via pandoc.
- Remove old LaTeX specification.

Co-authored-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

- Fix & test MemorySynthInit behavior with MemoryArrayInitAnnotation and MemoryScalarInitAnnotation.
Add test case for MemoryRandomInitAnnotation which is, on the contrary, expected not to leak any randomization statement in synthesis context.

- Refactor MemoryInitSpec for improved results readability

Context:

PR #2166 (commit: 4530152) introduced MemorySynthInit annotation to control whether statement generated with Memory*InitAnnotation (emitted within initial begin block in verilog) should be guarded with ifndef SYNTHESIS or not.
Unfortunately only one configuration (MemoryFileInlineAnnotation) has been tested while the others have been generating incorrect verilog statements (MemoryArrayInitAnnotation and MemoryScalarInitAnnotation).

Signed-off-by: Jean Bruant <jean.bruant@ovhcloud.com>

emission-options flags swapped to match their functionality

Verification statements are guarded by reset.
If this reset happens to be a "preset" type
reset, they should always be active.
The easiest way to achieve that is to replace
all uses of "preset" resets with zero.

This fixes an off by one error, where 3 was erroneously
accepted as in-bounds for a memory of depth=3

* Enable CI for 1.5.x branch
* Enable Mergify for 1.5.x branch
* Drop 1.2.x from Mergify

* Add FileInfo to asyncResetAlwaysBlocks

Always blocks need three FileInfo (if, true, false) to show line numbers,
but initially, every always blocks only have one FileInfo (false).

RemoveReset adds the extra two FileInfo to sync always blocks,
so sync always blocks can have line numbers.

Async always blocks don't provide their only FileInfo, so there are no line numbers.

This commit gives async always block the extra FileInfo to show line numbers for them.

This code:

```scala
import chisel3._
import chisel3.stage._
import firrtl.CustomDefaultRegisterEmission

class Test extends Module with RequireAsyncReset {
  val io = IO(new Bundle {
    val in = Input(Bool())
    val out = Output(Bool())
  })
  val valid = RegInit(false.B)
  valid := io.in
  io.out := valid
}

object Test extends App {
  new ChiselStage().execute(Array(), Seq(
    ChiselGeneratorAnnotation(() => new Test()),
    CustomDefaultRegisterEmission(useInitAsPreset = false, disableRandomization = true)
  ))
}
```

will generate this Verilog:

```verilog
module Test(
  input   clock,
  input   reset,
  input   io_in,
  output  io_out
);
  reg  valid; // @[Playground.scala 10:22]
  assign io_out = valid; // @[Playground.scala 12:10]
  always @(posedge clock or posedge reset) begin
    if (reset) begin // @[Playground.scala 10:22]
      valid <= 1'h0; // @[Playground.scala 10:22]
    end else begin
      valid <= io_in; // @[Playground.scala 11:9]
    end
  end
endmodule
```

they have correct line numbers (10, 10, 11).

* Add test for async always block line numbers

* Add comment for review

* Fix unreachable code warning by changing match order

Simulation Statements did not previously extend IsDeclaration, but now
they do so their match blocks need to be above IsDeclaration.

* Handle MemoryNoInit case in RtlilEmitter

* Remove use of deprecated logToFile

* Fix uses of LegalizeClocksTransform

Replaced all uses of LegalizeClocksTransform with
LegalizeClocksAndAsyncResetsTransform.

* Remove use of CircuitForm in ZeroWidth

Fix bugs related to arithmetic ops inlined into a mux leg.  Add formal
equivalence checks to lock in this behavior.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

This should fix issue #2436

* Add renamemap.MutableRenameMap which includes these methods without
  deprecation
* Deprecate Stringly typed RenameMap APIs which were accidentally
  undeprecated a while ago

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* Change AnnotationSeq underlying from List to Seq

It was nothing but pointless copying.

* Make propagateAnnotations faster

There was lots of expensive logic for very little benefit.

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1. Add CustomRadix{Def,Apply}Annotation to define and apply custom radix.
2. Add CustomRadixConfigFileAnnotation to output a JSON config file so
   users can generate scripts on their own.

Reviewed-by: Jiuyang Liu <liu@jiuyang.me>
Co-authored-by: sinofp <sinofp@tuta.io>

Improve ANTLR Parser

The ANTLR-generated concrete syntax tree (CST) takes up much more memory
than the parsed .fir file. By using a Listener, we can construct the
FIRRTL AST live with CST construction and null out the CST as we consume
pieces of it. Not only does this improve performance, it drastically
reduces max memory use for the parser.

Tweak the grammar to handle references without left-recursion. Also
split references and subreferences out from the regular expression rule
to make their parsing more efficient.