[chisel5] Purge Emitter, fix AddImpliictOutputFile

Rip out unused things from Emitter.scala.  Move the
AddImplicitOutputFile phase from firrtl to circt and update this to do
the right thing with a SplitVerilog annotation.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>