Implement Verilog output stream `PanamaCIRCTConverter` (#3520)

* Implement Verilog output stream `PanamaCIRCTConverter`

* Truncate or pad when connecting ports with different widths

* Use `scala.math.BigInt.bitLength` instead of our own `bitLength`

* Use correct module name for instances

* Binder introduces Firtool options

* fix binder for JDK21 and firtool 1.67.0

refer to:
- https://github.com/openjdk/jdk/pull/13079
- llvm-project/circt dadf87b742f547840f6866beb50bdf46a76d3fed

* fix for review

* reformat

* bump GitHub CI to JDK 21 and mill 0.11.5

* remove 2.13.0 to 2.13.10 for JDK21 in build.sc

ref to: https://github.com/scala/bug/issues/12783



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Co-authored-by: Jiuyang Liu <liu@jiuyang.me>