Skip to content
GitLab
Commit 66a72ff6 authored by Jack Koenig's avatar Jack Koenig Committed by Jack Koenig
Browse files

Add Analog type 

Used for stitching Verilog inout through Chisel Modules (from BlackBox
to BlackBox)
parent 132b80ed
Hide whitespace changes
Inline Side-by-side
Supports Markdown
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment