Enrich ShiftRegister with SyncReadMem-based implementation. (#2891)

Co-authored-by: Jiuyang Liu <liu@jiuyang.me>
Co-authored-by: Megan Wachs <megan@sifive.com>
Co-authored-by: Jack Koenig <koenig@sifive.com>
(cherry picked from commit 3382cab2)

# Conflicts:
#	src/test/scala/chiselTests/util/RegSpec.scala