Commit 2ef5c7e5 authored by Schuyler Eldridge's avatar Schuyler Eldridge
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Add chisel3.stage.phases.Convert Phase



This coalesces three distinct operations into one Convert Phase:

  1. Chisel Circuit to FIRRTL Circuit (CHIRRTL) conversion
  2. Conversion of Chisel Annotations to FIRRTL Annotations
  3. Generation of RunFirrtlTransformAnnotations

Signed-off-by: default avatarSchuyler Eldridge <schuyler.eldridge@ibm.com>
parent a26d0c4e
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