Improve Shl codegen; eliminate Shlw WIR node (#994)

* Improve Shl codegen; eliminate Shlw WIR node

If we emit shl(x, k) as {x, k'h0} instead of (x << k), then there's
no need for Verilog-specific padding in the PadWidths pass.  Avoiding
the redundant padding improves compiler/simulator performance and
renders Shlw unnecessary.

* [skip formal checks] Add test