- Aug 02, 2023
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Jiuyang Liu authored
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Jiuyang Liu authored
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Jiuyang Liu authored
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Jiuyang Liu authored
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- Jun 20, 2023
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Jiuyang Liu authored
Port fpga-shell to chisel3
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- Jun 19, 2023
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Porterlu authored
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- May 14, 2023
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Jiuyang Liu authored
Bump to latest rocketchip
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Jerry Zhao authored
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- Mar 21, 2023
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Jerry Zhao authored
Fold HasPeripheryDebugModuleImp into HasPeripheryDebug
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- Mar 08, 2023
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Jiuyang Liu authored
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- Mar 01, 2023
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- Feb 28, 2023
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Jerry Zhao authored
Fix LazyModuleImp compile error in AXKU040
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Jerry Zhao authored
FIX: replace chipsalliance.rocketchip to org.chipsalliance.cde
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singularity authored
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- Feb 27, 2023
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singularity authored
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- Feb 22, 2023
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Jiuyang Liu authored
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Ocean Shen authored
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- Feb 15, 2023
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Jerry Zhao authored
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- Feb 13, 2023
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Jerry Zhao authored
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- Feb 01, 2023
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Jerry Zhao authored
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- Jan 05, 2023
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Jerry Zhao authored
fix: chisel3 pr #2758
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- Dec 27, 2022
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SingularityKChen authored
+ Remove parenthesized forms of asClock(), asBool();
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- Nov 24, 2022
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Jerry Zhao authored
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- Nov 15, 2022
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Lori authored
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- Nov 08, 2022
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Ocean Shen authored
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- Sep 02, 2022
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Jerry Zhao authored
remove objectmodule
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Jerry Zhao authored
fix for chipsalliance/rocket-chip#2925
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Jerry Zhao authored
fix a bug introduced in 58bf5b37
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- Jun 06, 2022
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Jiuyang Liu authored
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- Jun 05, 2022
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Jiuyang Liu authored
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Jiuyang Liu authored
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- Jun 02, 2022
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Henry Cook authored
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Henry Cook authored
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Henry Cook authored
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Henry Cook authored
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- Dec 29, 2020
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Erik Danie authored
Add Xilinx IBUF_LOW_POWER property
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- Nov 15, 2020
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Connor Lee authored
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- Nov 11, 2020
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Abraham Gonzalez authored
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- Oct 29, 2020
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Henry Cook authored
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- Oct 20, 2020
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Erik Danie authored
Add Xilinx drive strength property
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