BundleBridge where source+sink are in the same module is unnecessary,
and is no longer supported in latest rocket-chip

Clean up FPGA Shell to support Chisel 3.6 and Chisel 5

Port fpga-shell to chisel3

Bump to latest rocketchip

Fold HasPeripheryDebugModuleImp into HasPeripheryDebug

https://github.com/chipsalliance/rocket-chip/commit/a2682ca382f5343f3478324ae2dbe7525582c7e1

Fix LazyModuleImp compile error in AXKU040

FIX: replace chipsalliance.rocketchip to org.chipsalliance.cde

fix: chisel3 pr #2758

+ Remove parenthesized forms of asClock(), asBool();

remove objectmodule

fix for chipsalliance/rocket-chip#2925

fix a bug introduced in 58bf5b37

Add Xilinx IBUF_LOW_POWER property