Set name of UART clock domain

Bump to latest rocket-chip | remove old HasDeviceModuleImp pattern

Update to match rocketchip APIs

REVERT: revert commit 20e36318

Recent versions of `firtool` flag these as "sink not fully initialized"
errors. See https://github.com/ucb-bar/chipyard/issues/1731 for more
context.

Update timer device to latest rocket-chip

Create TLWDTPeriphery.scala and fix mis-aligned widths in WatchdogTimer.scala

change maxcmp to be a protected def. Override maxcmp value in Watchdog timer. Add wdt periphery file, similar to other peripherals

Update to new rocket-chip APIs

Changed from channel 1 being sampled for single SPI mode

Update API for rocket-chip clusters API

Fix SPI bugs that were broken by Chisel2->Chisel3

* remove () from fire()
* add BlackBox
* remove IO and add BlackBox
* Port rocket-chip-blocks to chisel3
* remove NotStrictInferReset
* Remove GenericParameterizedBundle

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Co-authored-by: Jiuyang Liu <liu@jiuyang.me>
Co-authored-by: Porterlu <1258210724@qq.com>

Provide mechanism for accessing generated uarts