st-util: synchronize cache for stm32f7

This patch handles the cache on the cortex-m7 stm32f7 cpu.
When gdb inserts a soft breakpoint (which is the default for
code in RAM), it replaces an instruction with a breakpoint
instruction.  But if the caches are enabled, the replacement
may be made only in the D-cache.  To reach the I-cache, the
D-cache must be flushed and the I-cache invalidated.

This implementation is coarse: it cleans the whole D-cache
and invalidate the whole I-cache.  It is possible to
track which cache lines have to be cleaned and invalidated.